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psoc cy8ctmg20x, cy8ctmg20xa, cy8ctst200, cy8ctst200a trm psoc ? cy8ctmg20x, cy8ctmg20xa, cy8ctst200, cy8ctst200a technical reference manual (trm) document no. 001-53603 rev. *c december 11, 2009 cypress semiconductor 198 champion court san jose, ca 95134-1709 phone (usa): 800.858.1810 phone (intnl.): 408.943.2600 [+] feedback
2 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c copyrights copyrights ? cypress semiconductor corporation, 2009. the information co ntained herein is subject to change without notice. cypress semiconductor corporation assumes no res ponsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other righ ts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an expr ess written agreement with cypr ess. furthermore, cypress does not authorize its products for use as critical components in life- support systems where a malfunction or failur e may reasonably be ex pected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemnifies cypress against all charges. psoc? is a registered trademark and psoc designer?, truetouch?, and psoc express? are trademarks of cypress semiconductor corporation (cypress), along with cypress? and cypress semiconductor?. all other trademarks or regis- tered trademarks referenced herein are th e property of their respective owners. purchase of i 2 c components from cypress or one of its sublicensed associated companies convey s a license under the phil- ips i 2 c patent rights to use these components in an i 2 c system, provided that the sy stem conforms to the i 2 c standard specification as defined by philips. any source code (software and/or firmware) is owned by cypr ess semiconductor corporation (cypress) and is protected by and subject to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-e xclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and de rivative works for the sole pur pose of creating custom soft- ware and or firmware in support of licensee product to be used only in conjunction with a cypress integrated circuit as speci- fied in the applicable agreement. any reproduction, modificati on, translation, compilation, or representation of this source code except as specified above is prohibited wit hout the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this mate- rial, including, but not limited to, the implie d warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to the materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authorize its products fo r use as critical components in life-suppo rt systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? product in a life-support sys - tems application implies that the manufacturer assumes all ri sk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the app licable cypress software license agreement. flash code protection note the following details of the flash code protection features on cypress devices. cypress products meet the specifications co ntained in their particular cypress data sheets. cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be methods that can breach the c ode protection features. any of these methods, to our knowle dge, would be dishonest and pos- sibly illegal. neither cypress nor any other semiconductor ma nufacturer can guarantee the security of their code. code pro- tection does not mean that we are gu aranteeing the product as "unbreakable." cypress is willing to work with the custom er who is concerned about the integrity of their code. code prot ection is constantly evolving. we at cypress are committed to continuously improving the code pr otection features of our products. [+] feedback
3 contents overview section a: overview 13 1. pin information ............................................................................................................. ............. 19 section b: psoc core 23 2. cpu core (m8c) .............................................................................................................. .......... 27 3. supervisory rom (srom) ...................................................................................................... ... 33 4. ram paging.................................................................................................................. ............. 39 5. interrupt controller ........................................................................................................ ............. 45 6. general purpose i/o (gpio) .................................................................................................. .... 55 7. internal main oscillator (imo).............................................................................................. ....... 63 8. internal low speed oscillator (ilo) . ............... ............. .............. ............. ............ ........... .......... ... 67 9. external crystal oscillator (eco) ........................................................................................... .... 69 10. sleep and watchdog .......... .............. .............. ............. .............. ............. .............. ............. ......... 73 section c: truetouch system 83 11. truetouch module ........................................................................................................... .......... 85 12. i/o analog multiplexer .................................... ................................................................. ........... 99 13. comparators ................................................................................................................ ............ 101 section d: system resources 105 14. digital clocks ............................................................................................................. .............. 109 15. i2c slave .................................................................................................................. ............... 117 16. system resets .............................................................................................................. ........... 135 17. por and lvd ................................................................................................................ .......... 143 18. spi ........................................................................................................................ ................. 145 19. programmable timer ......................................................................................................... ....... 161 20. full-speed usb ............. ............. .............. .............. ........... ........... ............ ........... .......... .......... 165 section e: registers 183 21. register reference ......................................................................................................... ......... 187 section f: glossary 287 section f: index 303 [+] feedback
4 contents overview [+] feedback
5 contents section a: overview 13 1. pin information 19 1.1 pinouts..................................................................................................................... ...............19 1.1.1 cy8ctmg200-16lgxi, cy8ctmg2 00a-16lgxi, cy8ctst200-16lgxi, CY8CTST200A-16LGXI psoc 16-pin part pinout 19 1.1.2 cy8ctmg200-24lqxi, cy8ctmg2 00a-24lqxi, cy8ctst200-24lqxi, cy8ctst200a-24lqxi psoc 24-pin part pinout 20 1.1.3 cy8ctmg200-32lqxi, cy8ctmg2 00a-32lqxi, cy8ctst200-32lqxi, cy8ctst200a-32lqxi, cy8ctmg201-32lqxi, cy8ctmg201a-32lqxi psoc 32- pin part pinout21 1.1.4 cy8ctmg200-48ltxi, cy8ctmg200a-48ltxi, cy8ctst200-48ltxi, cy8ctst200a-48ltxi, cy8ctmg201-48ltxi, cy8ctmg201a-48ltxi psoc 48-pin part pinout22 section b: psoc core 23 2. cpu core (m8c) 27 2.1 overview.................................................................................................................... .............27 2.2 internal registers.......................................................................................................... ..........27 2.3 address spaces.............................................................................................................. ........27 2.4 instruction set summary ..................................................................................................... ...28 2.5 instruction formats ......................................................................................................... ........30 2.5.1 one-byte instructions ................................................................................................30 2.5.2 two-byte instructions ................................................................................................30 2.5.3 three-byte instructions..............................................................................................31 2.6 register definitions........................................................................................................ .........32 2.6.1 cpu_f register ........................................................................................................32 2.6.2 related registers ......................................................................................................32 3. supervisory rom (srom) 33 3.1 architectural description................................................................................................... ......33 3.1.1 additional srom feature ..........................................................................................34 3.1.2 srom function descriptions ....................................................................................34 3.1.2.1 swbootreset function ...............................................................................34 3.1.2.2 readblock function ....................................................................................35 3.1.2.3 writeblock function.....................................................................................35 3.1.2.4 eraseblock function....................................................................................36 3.1.2.5 protectblock function..................................................................................36 3.1.2.6 tableread function ....................................................................................36 3.1.2.7 eraseall function ........................................................................................36 3.1.2.8 checksum function.....................................................................................37 3.1.2.9 calibrate0 function .....................................................................................37 3.1.2.10 calibrate1 function .....................................................................................37 [+] feedback
6 contents 3.1.2.11 writeandverify function.............. ................................................................ 37 3.1.2.12 hwbootreset function............................................................................... 38 3.2 register definitions ........................................................................................................ ........ 38 4. ram paging 39 4.1 architectural description................................................................................................... ...... 39 4.1.1 basic paging.............................................................................................................. 39 4.1.2 stack operations ....................................................................................................... 40 4.1.3 interrupts ................................................................................................................ ... 40 4.1.4 mvi instructions......................................................................................................... 4 0 4.1.5 current page pointer................................................................................................. 40 4.1.6 index memory page pointer ...................................................................................... 41 4.2 register definitions ........................................................................................................ ........ 42 4.2.1 tmp_drx registers ................................................................................................. 42 4.2.2 cur_pp register ..................................................................................................... 42 4.2.3 stk_pp register ..................................................................................................... 43 4.2.4 idx_pp register ...................................................................................................... 43 4.2.5 mvr_pp register .................................................................................................... 43 4.2.6 mvw_pp register .................................................................................................... 44 4.2.7 related registers ...................................................................................................... 44 5. interrupt controller 45 5.1 architectural description................................................................................................... ...... 45 5.1.1 posted versus pending in terrupts ............................................................................. 46 5.2 application overview ........................................................................................................ ...... 46 5.3 register definitions ........................................................................................................ ........ 48 5.3.1 int_clr0 register .................................................................................................. 48 5.3.2 int_clr1 register ................................................................................................... 49 5.3.3 int_clr2 register .................................................................................................. 50 5.3.4 int_msk0 register................................................................................................... 51 5.3.5 int_msk1 register................................................................................................... 51 5.3.6 int_msk2 register................................................................................................... 52 5.3.7 int_sw_en register ............................................................................................... 52 5.3.8 int_vc register ...................................................................................................... 52 5.3.9 related registers ...................................................................................................... 53 6. general purpose i/o (gpio) 55 6.1 architectural description................................................................................................... ...... 55 6.1.1 general description................................................................................................... 56 6.1.2 digital i/o............................................................................................................... .... 56 6.1.3 analog and digital inputs........................................................................................... 56 6.1.4 port 1 distinctions...................................................................................................... 5 6 6.1.5 port 0 distinctions...................................................................................................... 5 7 6.1.6 gpio block interrupts................................................................................................ 57 6.1.6.1 interrupt modes ........................................................................................... 57 6.1.7 data bypass .............................................................................................................. 5 8 6.2 register definitions ........................................................................................................ ........ 59 6.2.1 prtxdr registers ................................................................................................... 59 6.2.2 prtxie registers ..................................................................................................... 59 6.2.3 prtxdmx registers ................................................................................................. 60 6.2.4 io_cfg1 register..................................................................................................... 61 6.2.5 io_cfg2 register..................................................................................................... 61 [+] feedback
7 contents 7. internal main oscillator (imo) 63 7.1 architectural description................................................................................................... ......63 7.2 application overview ........................................................................................................ ......63 7.2.1 trimming the imo ......................................................................................................63 7.2.2 engaging slow imo ...................................................................................................63 7.3 register definitions........................................................................................................ .........64 7.3.1 imo_tr register .......................................................................................................64 7.3.2 imo_tr1 register ....................................................................................................64 7.3.3 cpu_scr1 register .................................................................................................65 7.3.4 osc_cr2 register ...................................................................................................65 7.3.5 related registers ......................................................................................................66 8. internal low speed oscillator (ilo) 67 8.1 architectural description................................................................................................... ......67 8.2 register definitions........................................................................................................ .........68 8.2.1 ilo_tr register .......................................................................................................68 9. external crystal oscillator (eco) 69 9.1 architectural description................................................................................................... ......69 9.2 application overview ........................................................................................................ ......70 9.3 register definitions........................................................................................................ .........71 9.3.1 eco_enbus register .............................................................................................71 9.3.2 eco_trim register .................................................................................................71 9.3.3 eco_cfg register ..................................................................................................71 9.3.4 related registers ......................................................................................................72 10. sleep and watchdog 73 10.1 architectural description.................................................................................................. .......73 10.1.1 sleep control implementation logic ..........................................................................74 10.1.1.1 wakeup logic ..............................................................................................74 10.1.2 sleep timer.............................................................................................................. ..76 10.2 application overview ....................................................................................................... .......76 10.3 register definitions....................................................................................................... ..........77 10.3.1 res_wdt register ..................................................................................................77 10.3.2 slp_cfg register ...................................................................................................77 10.3.3 slp_cfg2 register .................................................................................................78 10.3.4 slp_cfg3 register .................................................................................................78 10.3.5 related registers ......................................................................................................78 10.4 timing diagrams........................................... ................................................................. .........79 10.4.1 sleep sequence ........................................................................................................79 10.4.2 wakeup sequence.....................................................................................................80 10.4.3 bandgap refresh .......................................................................................................80 10.4.4 watchdog timer.........................................................................................................81 section c: truetouch system 83 11. truetouch module 85 11.1 architectural description.................................................................................................. .......85 11.1.1 types of truetouch approaches ........... ....................................................................85 11.1.1.1 positive charge inte gration .........................................................................85 11.1.1.2 relaxation oscillato r....................................................................................86 11.1.1.3 successive approximat ion ..........................................................................87 11.1.1.4 negative char ge integration........................................................................88 [+] feedback
8 contents 11.1.1.5 sigma delta................................................................................................. 89 11.1.2 idac ..................................................................................................................... ..... 90 11.1.3 truetouch counter ................................................................................................... 90 11.1.3.1 operation .................................................................................................... 91 11.2 register definitions ...................................................................................................... ......... 92 11.2.1 cs_cr0 register ................................. .................................................................... 92 11.2.2 cs_cr1 register ................................. .................................................................... 93 11.2.3 cs_cr2 register ................................. .................................................................... 93 11.2.4 cs_cr3 register ................................. .................................................................... 94 11.2.5 cs_cntl register ................................................................................................... 94 11.2.6 cs_cnth register ........ .......................................................................................... 94 11.2.7 cs_stat register ................................................................................................... 95 11.2.8 cs_timer register ............................. .................................................................... 95 11.2.9 cs_slew register .................................................................................................. 96 11.2.10 prs_cr register ..................................................................................................... 96 11.2.11 idac_d register ...................................................................................................... 97 11.3 timing diagrams .......................................... .................................................................. ........ 97 12. i/o analog multiplexer 99 12.1 architectural description.................................................................................................. ....... 99 12.2 register definitions ....................................................................................................... .......100 12.2.1 mux_crx registers .......... .....................................................................................100 13. comparators 101 13.1 architectural description . ................................................................................................ .....101 13.2 register definitions ...................................................................................................... .......103 13.2.1 cmp_rdc register ...............................................................................................103 13.2.2 cmp_mux register ................................. ..............................................................103 13.2.3 cmp_cr0 register ........ ........................................................................................104 13.2.4 cmp_cr1 register ........ ........................................................................................104 13.2.5 cmp_lut register ................................................................................................104 section d: system resources 105 14. digital clocks 109 14.1 architectural description.................................................................................................. .....109 14.1.1 internal main oscillator............................................................................................109 14.1.2 internal low speed osc illator.................................................................................. 110 14.1.3 external clock ......................................................................................................... 11 0 14.1.3.1 switch operation ......................... ..............................................................110 14.2 register definitions ....................................................................................................... .......112 14.2.1 usb_misc_cr register .......................... .............................................................. 112 14.2.2 out_p0 register ................................................................................................... 113 14.2.3 out_p1 register ................................................................................................... 113 14.2.4 osc_cr0 register ................................................................................................ 113 14.2.5 osc_cr2 register ................................................................................................ 115 15. i2c slave 117 15.1 architectural description.................................................................................................. .....117 15.1.1 basic i2c data transfer .......................................................................................... 118 15.2 application overview ....................................................................................................... .....118 15.2.1 slave operation....................................................................................................... 118 15.2.2 ezi2c mode ....................... ..................................................................................... 119 [+] feedback
9 contents 15.3 register definitions....................................................................................................... ........122 15.3.1 i2c_xcfg register ........ .........................................................................................122 15.3.2 i2c_xstat register................................................................................................123 15.3.3 i2c_addr register........ .........................................................................................123 15.3.4 i2c_bp register ......................................................................................................123 15.3.5 i2c_cp register .................................... ..................................................................124 15.3.6 cpu_bp register ....................................................................................................124 15.3.7 cpu_cp register....................................................................................................124 15.3.8 i2c_buf register....................................................................................................125 15.3.9 i2c_cfg register ..................................................................................................126 15.3.10 i2c_scr register ......... .........................................................................................128 15.3.11 i2c_dr register .....................................................................................................129 15.4 timing diagrams........................................... ................................................................. .......130 15.4.1 clock generation ................ .....................................................................................130 15.4.2 basic i/o timing.......................................................................................................13 0 15.4.3 status timing ...........................................................................................................1 31 15.4.4 slave stall timing ....................................................................................................132 15.4.5 implementation ........................................................................................................132 15.4.6 compatibility mode config uration ............................................................................133 16. system resets 135 16.1 architectural description.................................................................................................. .....135 16.2 pin behavior during reset ....................... ........................................................................... .135 16.2.1 gpio behavior on power up...................................................................................135 16.2.2 powerup external reset behavior ...........................................................................136 16.2.3 gpio behavior on external reset ...........................................................................136 16.3 register definitions....................................................................................................... ........137 16.3.1 cpu_scr1 register ...............................................................................................137 16.3.2 cpu_scr0 register ...............................................................................................138 16.4 timing diagrams........................................... ................................................................. .......139 16.4.1 power on reset . .....................................................................................................139 16.4.2 external reset .........................................................................................................13 9 16.4.3 watchdog timer reset ............................. ...............................................................139 16.4.4 reset details ...........................................................................................................1 41 16.5 power modes................................................................................................................ ........141 17. por and lvd 143 17.1 architectural description.................................................................................................. .....143 17.2 register definitions....................................................................................................... ........144 17.2.1 vlt_cr register .....................................................................................................144 17.2.2 vlt_cmp register ..................................................................................................144 18. spi 145 18.1 architectural description.................................................................................................. .....145 18.1.1 spi protocol function ..............................................................................................145 18.1.1.1 spi protocol signal definitions..................................................................146 18.1.2 spi master function .... ............................................................................................146 18.1.2.1 usability exceptions ... ...............................................................................146 18.1.2.2 block interrupt ...........................................................................................146 18.1.3 spi slave function ..................................................................................................146 18.1.3.1 usability exceptions ... ...............................................................................146 18.1.3.2 block interrupt ...........................................................................................147 18.1.4 input synchronization .. ............................................................................................147 [+] feedback
10 contents 18.2 register definitions ....................................................................................................... .......147 18.2.1 spi_txr register ...................................................................................................147 18.2.2 spi_rxr register...................................................................................................148 18.2.2.1 spi master da ta register definitions........................................................148 18.2.2.2 spi slave data register definiti ons..........................................................148 18.2.3 spi_cr register .....................................................................................................149 18.2.3.1 spi control register definitions.. ..............................................................149 18.2.4 spi_cfg register...................................................................................................150 18.2.4.1 spi configuration re gister definitions ......................................................150 18.2.5 related registers ....................................................................................................150 18.3 timing diagrams .......................................... .................................................................. ......151 18.3.1 spi mode timing .....................................................................................................151 18.3.2 spim timing ............................................................................................................15 2 18.3.3 spis timing.............................................................................................................1 57 19. programmable timer 161 19.1 architectural description.................................................................................................. .....161 19.1.1 operation................................................................................................................ .161 19.2 register definitions ....................................................................................................... .......163 19.2.1 pt0_cfg register ............. .....................................................................................163 19.2.2 pt1_cfg register ............. .....................................................................................163 19.2.3 pt2_cfg register ............. .....................................................................................164 19.2.4 ptx_data0 register...............................................................................................164 19.2.5 ptx_data1 register...............................................................................................164 20. full-speed usb 165 20.1 architectural description.................................................................................................. .....165 20.2 application description .................................................................................................... .....165 20.2.1 usb sie .................................................................................................................. 165 20.2.2 usb sram..............................................................................................................166 20.2.2.1 psoc memory arbiter ...............................................................................166 20.2.3 oscillator lock .........................................................................................................1 68 20.2.4 transceiver .............................................................................................................. 168 20.2.5 usb suspend ..........................................................................................................168 20.2.5.1 using standby i2c-usb sleep mode for usb suspend...........................169 20.2.5.2 using standby or deep sleep m odes for usb suspend ..........................169 20.2.5.3 wakeup from suspend ..............................................................................169 20.2.6 regulator .. .............................................................................................................. .169 20.3 register definitions ....................................................................................................... .......171 20.3.1 usb_sof0 register ...............................................................................................171 20.3.2 usb_cr0 register..................................................................................................171 20.3.3 usbio_cr0 register..............................................................................................172 20.3.4 usbio_cr1 register..............................................................................................172 20.3.5 ep0_cr register ....................................................................................................173 20.3.6 ep0_cnt register ............. .....................................................................................174 20.3.7 ep0_drx register ..................................................................................................174 20.3.8 epx_cnt1 register ................................................................................................175 20.3.9 epx_cnt0 register ................................................................................................176 20.3.10 epx_cr0 register ..................................................................................................177 20.3.11 pmax_wa register .................................................................................................178 20.3.12 pmax_dr register .................................................................................................179 20.3.13 pmax_ra register.......... ........................................................................................180 20.3.14 usb_cr1 register..................................................................................................180 [+] feedback
11 contents 20.3.15 imo_tr1 register................................. ..................................................................181 20.3.16 related registers ....................................................................................................181 section e: registers 183 21. register reference 187 21.1 maneuvering around the registers ......................................................................................187 21.2 register conventions ....................................................................................................... ....187 21.3 bank 0 registers ...................................... ..................................................................... .......188 21.3.1 prtxdr .................................................................................................................. 188 21.3.2 prtxie .................................................................................................................. .189 21.3.3 spi_txr ................................................................................................................. 190 21.3.4 spi_rxr ................................................................................................................1 91 21.3.5 spi_cr .................................................................................................................. .192 21.3.6 usb_sof0 .............................................................................................................193 21.3.7 usb_sof1 .............................................................................................................194 21.3.8 usb_cr0 ...............................................................................................................19 5 21.3.9 usbio_cr0 ...........................................................................................................196 21.3.10 usbio_cr1 ...................... .....................................................................................197 21.3.11 ep0_cr ................................................................................................................. .198 21.3.12 ep0_cnt .................... ............................................................................................ 199 21.3.13 ep0_drx ................................................................................................................ 200 21.3.14 epx_cnt0 ..............................................................................................................2 01 21.3.15 epx_cnt1 ..............................................................................................................2 02 21.3.16 pmax_dr ............................................. ..................................................................2 03 21.3.17 amux_cfg ....................... .....................................................................................204 21.3.18 cmp_rdc ............................................... ...............................................................20 5 21.3.19 cmp_mux ..............................................................................................................20 6 21.3.20 cmp_cr0 .......... .....................................................................................................2 07 21.3.21 cmp_cr1 .......... .....................................................................................................2 08 21.3.22 cmp_lut ...............................................................................................................2 10 21.3.23 cs_cr0 ...................... ........................................................................................... .211 21.3.24 cs_cr1 ...................... ........................................................................................... .212 21.3.25 cs_cr2 ...................... ........................................................................................... .213 21.3.26 cs_cr3 ...................... ........................................................................................... .214 21.3.27 cs_cntl ...................... .........................................................................................2 15 21.3.28 cs_cnth ...................... .........................................................................................2 16 21.3.29 cs_stat ....... ......................................................................................................... 217 21.3.30 cs_timer ............................................ ..................................................................2 18 21.3.31 cs_slew .......... .....................................................................................................2 19 21.3.32 prs_cr ................................................................................................................. 220 21.3.33 pt0_cfg ................................................................................................................ 221 21.3.34 ptx_data1 ................... .........................................................................................22 2 21.3.35 ptx_data0 ................... .........................................................................................22 3 21.3.36 pt1_cfg ................................................................................................................ 224 21.3.37 pt2_cfg ................................................................................................................ 225 21.3.38 i2c_xcfg ............................................ ..................................................................2 26 21.3.39 i2c_xstat .... .........................................................................................................2 27 21.3.40 i2c_addr ..............................................................................................................2 28 21.3.41 i2c_bp ................................................................................................................. ..229 21.3.42 i2c_cp ................................................................................................................. ..230 21.3.43 cpu_bp ................................................................................................................. 231 21.3.44 cpu_cp ................................................................................................................. 232 21.3.45 i2c_buf ............................................ .................................................................... .233 [+] feedback
12 contents 21.3.46 cur_pp ................................................................................................................. 234 21.3.47 stk_pp ................................................................................................................. .235 21.3.48 idx_pp ................................................................................................................. ..236 21.3.49 mvr_pp ................................................................................................................. 237 21.3.50 mvw_pp .............................................. ..................................................................2 38 21.3.51 i2c_cfg ................................................................................................................ 239 21.3.52 i2c_scr ................................................................................................................ 240 21.3.53 i2c_dr ................................................................................................................. ..241 21.3.54 int_clr0 ............................................................................................................... 242 21.3.55 int_clr1 ............................................................................................................... 244 21.3.56 int_clr2 ............................................................................................................... 246 21.3.57 int_msk2 ...................... ........................................................................................2 48 21.3.58 int_msk1 ...................... ........................................................................................2 49 21.3.59 int_msk0 ...................... ........................................................................................2 50 21.3.60 int_sw_en ................... ........................................................................................251 21.3.61 int_vc .............................................. ................................................................... ..252 21.3.62 res_wdt ..............................................................................................................25 3 21.3.63 cpu_f .................................................................................................................. ..254 21.3.64 idac_d ................................................................................................................. .256 21.3.65 cpu_scr1 ............................................................................................................257 21.3.66 cpu_scr0 ............................................................................................................258 21.4 bank 1 registers ....................................... .................................................................... .......259 21.4.1 prtxdm0 ...............................................................................................................25 9 21.4.2 prtxdm1 ...............................................................................................................26 0 21.4.3 spi_cfg ................................................................................................................2 61 21.4.4 usb_cr1 ...............................................................................................................26 2 21.4.5 pmax_wa ..............................................................................................................263 21.4.6 pmax_ra ...............................................................................................................26 4 21.4.7 epx_cr0 ................................................................................................................2 65 21.4.8 tmp_drx ...............................................................................................................26 6 21.4.9 usb_misc_cr ......................................................................................................267 21.4.10 out_p0 ................................................................................................................. .268 21.4.11 eco_enbus .........................................................................................................269 21.4.12 eco_trim .............................................................................................................27 0 21.4.13 mux_crx ............................................. ..................................................................2 71 21.4.14 io_cfg1 ................................................................................................................ 272 21.4.15 out_p1 ................................................................................................................. .273 21.4.16 io_cfg2 ................................................................................................................ 275 21.4.17 osc_cr0 ...............................................................................................................2 76 21.4.18 eco_cfg ..............................................................................................................27 7 21.4.19 osc_cr2 ...............................................................................................................2 78 21.4.20 vlt_cr ................................................................................................................. .279 21.4.21 vlt_cmp ...............................................................................................................2 80 21.4.22 imo_tr ................................................................................................................. .281 21.4.23 ilo_tr ................................................................................................................. ..282 21.4.24 slp_cfg ...............................................................................................................2 83 21.4.25 slp_cfg2 .............................................................................................................28 4 21.4.26 slp_cfg3 .............................................................................................................28 5 21.4.27 imo_tr1 ..................... ........................................................................................... 286 section f: glossary 287 section f: index 303 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 13 section a: overview the psoc ? family consists of many programmable system-on-ch ip with on-chip controller devices. the cy8ctmg20x and cy8ctst200 psoc devices have fixed analog and digital resources in addition to a fast cpu, flash program memory, and sram data memory to support various truetouch? algorithms. for the most up-to-date ordering, pinout, packaging, or electr ical specification information, refer to the psoc device?s data sheet. for the most current technical reference manual info rmation and newest product documentation, go to the cypress web site at http://www.cypress.com >> documentation. this section contains: pin information on page 19 . document organization this manual is organized into sections and chapters, according to psoc functionality. each section contains a top-level archi- tectural diagram and a register summary (if applicable). most chapters within the sections hav e an introduction, an architec- tural/application description, register definitions, and timing diagrams. the sections are as follows: overview ? presents the top-level architecture, helpful in formation to get started, and document history and conventions. the psoc device pinouts are detailed in the chapter pin information, on page 19 . psoc core ? describes the heart of the psoc device in various ch apters, beginning with an arch itectural overview and a summary list of registers pertaining to the psoc core. truetouch system ? describes the configurable psoc truetouch syst em in various chapters, beginning with an archi- tectural overview and a summ ary list of registers pertai ning to the truetouch system. system resources ? presents additio nal psoc system resources, beginning with an overview and a summary list of registers pertaining to system resources. registers ? lists all psoc device registers in register mapping tables , and presents bit-level detail of each register in its own register reference chapter. where applicable, detailed register descriptions are also located in each chapter. glossary ? defines the specialized terminology used in this manual. glossary terms are presented in bold, italic font throughout this manual. index ? lists the location of key topics and elements that constitute and empower the psoc devices. [+] feedback
14 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section a: overview top level architecture the psoc block diagram on the next page illustrates the top-level architecture of the cy8ctmg20x and cy8ctst200 devices. each major grouping in the diagram is covered in this manual in its own section: psoc core, truetouch system, and the system resources. banding these three main areas togeth er is the communication net- work of the system bus . psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses the sram for data storage, an interrupt controller for easy program execution to new addresses, sleep and watchdog timers, a regulated 3.0v output option is provided for port 1 i/os, and multiple clock sources that include the imo (internal main oscillator) and ilo (internal low speed oscillator) for precision, programma- ble clocking. the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four mips 8- bit har- vard architecture microprocessor. within the cpu core are the srom and flash memory components that provide flexible programming. psoc gpios provide connection to the cpu and the true- touch resources of the device. each pin?s drive mode is selectable from four options , allowing great flexibility in external interfacing. every pin also has the capability to gen- erate a system interrupt on low level and change from last read. truetouch? system the truetouch system is comp osed of comparators, refer- ence drivers, i/o multiplexers, and digital logic to support various capacitive sensing algorithms. various reference selections are provided. digital logic is mainly comprised of counters and timers. system resources the system resources provide additional psoccapability. these system resources include: digital clocks to increase the flexibility of the psoc pro- grammable system-on-chip. i2c functionality with "no bus stalling.? various system resets supported by the m8c. power-on-reset (por) circuit protection. spi master and slave functionality. a programmable timer to provide periodic interrupts. clock boost network providing a stronger signal to switches. full-speed usb interface for usb 2.0 communication with 512 bytes of dedicated buffer memory and an inter- nal 3v regulator. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 15 section a: overview psoc core top-level block diagram 1k, 2k sram interrupt controller sleep and watchdog multiple clock sources internal low speed oscillator (ilo) 6/12/24 mhz internal main oscillator (imo) core cpu core (m8c) supervisory rom (srom) 8k, 16k, 32k flash nonvolatile memory system resources system bus system bus port 3 port 2 port 1 port 0 1.8/2.5/3v ldo i2c slave spi master/ slave por and lvd usb system resets three 16-bit programmable timers pwrsys (regulator) port 4 digital clocks [+] feedback
16 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section a: overview getting started the quickest path to understanding psoc is by reading the psoc device?s data sheet and using psoc designer? integrated development environment (ide) . this manual is useful for understanding the details of the psoc integrated circuit. important note for the most up-to-date ordering, packaging, or electric al specification informati on, refer to the individual psoc device?s data sheet or go to http://www.cypress.com . support free support for psoc products is available online at http://www.cypress.com. resources include trai ning seminars, discus- sion forums, application notes, tightlink technical suppor t email/knowledge base, and application support technicians. technical support can be reached at http://www.cypress.com/support. product upgrades cypress provides scheduled upgrades and version enhancemen ts for psoc designer free of charge. you can order the upgrades from your distributor on cd- rom or download them directly from http://www.cypress.com under software. also pro- vided are critical updates to system documentation under http://www.cypress.com >> documentation . development kits the cypress online store contains development kits, c compilers, and all accessories fo r psoc development. go to the cypress online store web site at http://www.cypress.com under order >> psoc kits. document history this section serves as a chronicle of the psoc? cy8ctmg20x, cy8ctmg20xa, cy8ctst200, cy8ctst200a technical reference manual . technical reference manual history version/ release date originator description of change ** may 2009 dsg first release of the cy8ctmg20x, cy8ctst200 technical reference manual. *a august 2009 dsg second release of the cy8ctmg20x, cy8ctst200 technical reference manual. *b november 2009 fsu multiple fixes, primarily to the sleep and i2c chapters. *c december 2009 fsu multiple fixes, primarily to the external crystal oscillator chapter. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 17 section a: overview documentation conventions there are only four distinguish ing font types used in this manual, besides those found in the headings. the first is the use of italics when referencing a docu- ment title or file name. the second is the use of bold italics when referencing a term described in the glossary of this manual. the third is the use of times new roman font, distinguish- ing equation examples. the fourth is the use of courier new font, distinguish- ing code examples. register conventions the following table lists the re gister conventions that are specific to this manual. a more detailed set of register con- ventions is located in the register reference chapter on page 187 . numeric naming hexadecimal numbers are repr esented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?) and hexadecimal numbers may also be rep- resented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimal . units of measure this table lists the units of measure used in this manual. register conventions convention example description ?x? in a register name prtxie multiple instances/address ranges of the same register r r : 00 read register or bit(s) w w : 00 write register or bit(s) o ro : 00 only a read/write register or bit(s). l rl : 00 logical register or bit(s) c rc : 00 clearable register or bit(s) 00 rw : 00 reset value is 0x00 or 00h xx rw : xx register is not reset 0, 0,04h register is in bank 0 1, 1,23h register is in bank 1 x, x,f7h register exists in register bank 0 and reg- ister bank 1 empty, grayed- out table cell reserved bit or group of bits, unless oth- erwise stated units of measure symbol unit of measure c degree celsius db decibels ff femtofarad hz hertz k kilo, 1000 k 2 10 , 1024 kb 1024 bytes kbit 1024 bits khz kilohertz (32.000) k kilohm mhz megahertz m megaohm a microampere f microfarad s microsecond v microvolt vrms microvolts root-mean-square ma milliampere ms millisecond mv millivolt na nanoamphere ns nanosecond nv nanovolt ohm pf picofarad pp peak-to-peak ppm parts per million sps samples per second sigma: one standard deviation v volt [+] feedback
18 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section a: overview acronyms this table lists the acronyms that are used in this manual. acronyms acronym description abus analog output bus ac alternating current adc analog-to-digital converter api application programming interface bc broadcast clock br bit rate bra bus request acknowledge brq bus request cbus comparator bus ci carry in cmp compare co carry out cpu central processing unit crc cyclic redundancy check ct continuous time dac digital-to-analog converter dc direct current di digital or data input dma direct memory access do digital or data output eco external crystal oscillator fb feedback gie global interrupt enable gpio general purpose i/o ice in-circuit emulator ide integrated development environment ilo internal low speed oscillator imo internal main oscillator i/o input/output ior i/o read iow i/o write ipor imprecise power on reset irq interrupt request isr interrupt service routine issp in system serial programming ivr interrupt vector read lfsr linear feedback shift register lrb last received bit lrb last received byte lsb least significant bit lsb least significant byte lut look-up table miso master-in-slave-out mosi master-out-slave-in msb most significant bit msb most significant byte pc program counter pch program counter high pcl program counter low pd power down pma psoc? memory arbiter por power on reset ppor precision power on reset prs pseudo random sequence psoc? programmable system-on-chip pssdc power system sleep duty cycle pwm pulse width modulator ram random access memory reti return from interrupt ro relaxation oscillator rom read only memory rw read/write sar successive approximation register sc switched capacitor sie serial interface engine se0 single-ended zero sof start of frame sp stack pointer spi serial peripheral interconnect spim serial peripheral interconnect master spis serial peripheral interconnect slave sram static random access memory srom supervisory read only memory ssadc single slope adc ssc supervisory system call tc terminal count usb universal serial bus wdt watchdog timer wdr watchdog reset xres external reset acronyms (continued) acronym description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 19 1. pin information this chapter lists, describes, and illustrates all pins and pinout configurations for the cy8ctmg20x, cy8ctmg20xa, cy8ctst200, and cy8ctst200a psoc devices. for up-to-date or dering, pinout, and packaging information, refer to the individual psoc device?s data sheet or go to http://www.cypress.com . 1.1 pinouts the cy8ctmg20x, cy8ctmg20xa, cy8ctst200, and cy8ctst200a psoc devices are available in a variety of pack- ages. every port pin (labeled with a ?p?), except for vss , vdd , and xres in the following tables and illustrations, is capable of digital i/o. 1.1.1 cy8ctmg200-16lgx i, cy8ctmg200a-16lgxi, cy8ctst200-16lgxi, CY8CTST200A-16LGXI psoc 16-pin part pinout table 1-1. 16-pin qfn/col part pinout pin no. type name description cy8ctmg200-16lgxi, cy8ctmg200a-16lgxi, cy8ctst200-16lgxi CY8CTST200A-16LGXI psoc devices digital analog 1 io i p2[5] xtal out 2 io i p2[3] xtal in 3 iohr i p1[7] i2c scl, spi ss 4 iohr i p1[5] i2c sda, spi miso 5 iohr i p1[3] spi clk 6 iohr i p1[1] tc clk*, i2c scl, spi mosi 7 power vss ground pin 8 iohr i p1[0] tc data*, i2c sda, spi clk 9 iohr i p1[2] 10 iohr i p1[4] extclk 11 input xres active high external reset with internal pull down 12 ioh i p0[4] 13 power vdd power pin 14 ioh i p0[7] 15 ioh i p0[3] integrating input 16 ioh i p0[1] integrating input legend a = analog, i = input, o = output, h = 5 ma high output drive, r = regulated output option. * these are the issp pins, which are not high z at por (power on reset). p2[5] p1[7] p1[5] p1[3] p0[3] p0[7] vdd p0[4] p1[1] p1[0] p1[2] p2[3] p1[4] xres p0[1] vss qfn (top view) 1 2 3 4 12 11 10 9 16 15 14 13 5 6 7 8 [+] feedback
20 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c pin information 1.1.2 cy8ctmg200-24lqxi, cy8ctmg2 00a-24lqxi, cy8ctst200-24lqxi, cy8ctst200a-24lqxi psoc 24-pin part pinout table 1-2. 24-pin qfn part pinout ** pin no. type name description cy8ctmg200-24lqxi, cy 8ctmg200a-24lqxi, cy8ctst200-24lqxi, cy8ctst200-24lqxi psoc device digital analog 1 io i p2[5] xtal out 2 io i p2[3] xtal in 3 io i p2[1] 4 iohr i p1[7] i2c scl, spi ss 5 iohr i p1[5] i2c sda, spi miso 6 iohr i p1[3] spi clk 7 iohr i p1[1] tc clk*, i2c scl, spi mosi 8 nc no connection 9 power vss ground pin 10 iohr i p1[0] tc data*, i2c sda, spi clk 11 iohr i p1[2] 12 iohr i p1[4] extclk 13 iohr i p1[6] 14 input xres active high external reset with internal pull down 15 io i p2[0] 16 ioh i p0[0] 17 ioh i p0[2] 18 ioh i p0[4] 19 ioh i p0[6] 20 power vdd power pin 21 ioh i p0[7] 22 ioh i p0[5] 23 ioh i p0[3] integrating input 24 ioh i p0[1] integrating input legend a = analog, i = input, o = output, h = 5 ma high output drive, r = regulated output option. * these are the issp pins, which are not high z at por (power on reset). ** the center pad on the qfn package must be connected to ground (vss) for best mechanical, thermal, and electrical performance. if not con- nected to ground, it must be electrically floated and not connected to any other signal. qfn (top view) p2[5] p1[7] p1[5] p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[2] p0[0] 24 23 22 21 20 19 p0[3] p0[5] p0[7] vdd p0[4] 7 8 9 10 11 12 p1[1] p1[0] p1[2] p2[3] p2[1] nc p1[6] p1[4] xres p2[0] p0[6] p0[1] vss [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 21 pin information 1.1.3 cy8ctmg200-32lqx i, cy8ctmg200a-32lqxi, cy8ctst200-32lqxi, cy8ctst200a-32lqxi, cy8ctmg201-32l qxi, cy8ctmg201a-32lqxi psoc 32-pin part pinout table 1-3. 32-pin qfn part pinout ** pin no. digital analog name description cy8ctmg200-32lqxi, cy8ctmg200a-32lqxi, cy8ctst200-32lqxi, cy8ctst200a-32lqxi, cy8ctmg201-32lqxi, cy8ctmg201a-32lqxi psoc devices 1 ioh i p0[1] integrating input 2 io i p2[7] 3 io i p2[5] xtal out 4 io i p2[3] xtal in 5 io i p2[1] 6 io i p3[3] 7 io i p3[1] 8 iohr i p1[7] i2c scl, spi ss 9 iohr i p1[5] i2c sda, spi miso 10 iohr i p1[3] spi clk 11 iohr i p1[1] tc clk*, i2c scl, spi mosi 12 power vss ground pin 13 iohr i p1[0] tc data*, i2c sda, spi clk 14 iohr i p1[2] 15 iohr i p1[4] extclk 16 iohr i p1[6] 17 input xres active high external reset with internal pull down 18 io i p3[0] 19 io i p3[2] 20 io i p2[0] 21 io i p2[2] 22 io i p2[4] 23 io i p2[6] 24 ioh i p0[0] 25 ioh i p0[2] 26 ioh i p0[4] 27 ioh i p0[6] 28 power vdd power pin 29 ioh i p0[7] 30 ioh i p0[5] 31 ioh i p0[3] 32 power vss ground pin legend a = analog, i = input, o = output, nc = no connection, h = 5 ma high output drive, r = regulated output option. * issp pin which is not high z at por (power on reset). ** the center pad on the qfn package must be connected to ground (vss) for best mechanical, thermal, and electrical performance . if not connected to ground, it must be electrically floated and not connected to any other signal. p0[1] p2[7] p2[5] p2[3] p2[1] p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3] p0[7] vdd p0[6] p0[4] p0[2] p3[1] p1[7] p0[0] p2[6] p3[0] xres p1[5] p1[3] p1[1] vss p1[0] p1[2] p1[4] p1[6] p2[4] p2[2] p2[0] p3[2] p0[5] [+] feedback
22 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c pin information 1.1.4 cy8ctmg200-48ltxi, cy8ctmg2 00a-48ltxi, cy8ctst200-48ltxi, cy8ctst200a-48ltxi, cy8ctmg201-48l txi, cy8ctmg201a-48ltxi psoc 48-pin part pinout table 1-4. 48-pin part pinout ** pin no. digital analog name description cy8ctmg200-48ltxi, cy8ctmg200a-48ltxi, cy8ctst200-48ltxi, cy8ctst200a-48ltxi, cy8ctmg201-48ltxi, cy8ctmg201a-48ltxi psoc devices 1 nc no connection 2 io i p2[7] 3 io i p2[5] xtal out 4 io i p2[3] xtal in 5 io i p2[1] 6 io i p4[3] 7 io i p4[1] 8 io i p3[7] 9 io i p3[5] 10 io i p3[3] 11 io i p3[1] 12 iohr i p1[7] i2c scl, spi ss 13 iohr i p1[5] i2c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] tc clk*, i2c scl, spi mosi 18 power vss ground pin 19 io d + usb phy 20 io d - usb phy 21 power vdd power pin 22 iohr i p1[0] tc data*, i2c sda, spi clk 23 iohr i p1[2] 24 iohr i p1[4] extclk 25 iohr i p1[6] 26 input xres active high external reset with internal pull down 27 io i p3[0] 28 io i p3[2] 29 io i p3[4] 30 io i p3[6] pin no. digital analog name description 31 io i p4[0] 32 io i p4[2] 33 io i p2[0] 41 power vdd power pin 34 io i p2[2] 42 nc no connection 35 io i p2[4] 43 nc no connection 36 io i p2[6] 44 ioh i p0[7] 37 ioh i p0[0] 45 ioh i p0[5] 38 ioh i p0[2] 46 ioh i p0[3] integrating input 39 ioh i p0[4] 47 power vss ground pin 40 ioh i p0[6] 48 ioh i p0[1] integrating input legend a = analog, i = input, o = output, nc = no connection, h = 5 ma high output drive, r = regulated output option. * issp pin which is not high z at por (power on reset). ** the center pad on the qfn package must be connected to ground (vss) for best mechanical, thermal, and electrical performance . if not connected to ground, it must be electrically floated and not connected to any other signal. qfn (top view) p0[1] vss p0[3] p0[5] p0[7] nc nc vdd p0[6] p0[4] p0[2] p0[0] 10 11 12 p2[7] nc p2[5] p2[3] p2[1] p4[3] p4[1] p3[7] p3[5] p3[3] p3[1] p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4] p2[2] p2[0] p4[2] p4[0] p3[6] p3[4] p3[2] p3[0] xres p1[6] p2[6] 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 p1[5] nc nc p1[3] p1[1] vss d+ d- vdd p1[0] p1[2] p1[4] [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 23 section b: psoc core the psoc core section discusses the core components of a psoc device with a base part number of cy8ctmg20x or cy8ctst200 and the registers associated with those components. the core sect ion covers the heart of the psoc device, which includes the m8c microcontroller ; srom, interrupt controller, gpio, and sram paging; multiple clock sources such as imo and ilo; and sleep and watchdog function ality. this section includes these chapters: cpu core (m8c) on page 27 . supervisory rom (srom) on page 33 . ram paging on page 39 . interrupt controller on page 45 . general purpose i/o (gpio) on page 55 . internal main oscillator (imo) on page 63 . internal low speed oscillator (ilo) on page 67 . external crystal oscillator (eco), on page 69 sleep and watchdog on page 73 . top-level core architecture this figure displays the top level architecture of the psoc core . each component of the figure is discussed at length in this section. psoc core block diagram 1k, 2k sram interrupt controller sleep and watchdog multiple clock sources internal low speed oscillator (ilo) 6/12/24 mhz internal main oscillator (imo) core cpu core (m8c) supervisory rom (srom) 8k, 16k, 32k flash nonvolatile memory system bus port 3 port 2 port 1 port 0 1.8/2.5/3v ldo pwrsys (regulator) port 4 [+] feedback
24 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section b: psoc core core register summary this table lists all the psoc registers for the cpu core in address order within their system re source configuration. the grayed out bits are reserved bits. if you write these bits always write them with a value of ?0?. for the core registers, the f irst ?x? in some register addresses represents either bank 0 or bank 1. these registers are listed throughout this manual in bank 0, even though they are also available in bank 1. summary table of the core registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access m8c register (page 27 ) x,f7h cpu_f pgmode[1:0] xio_1 xio carry zero gie rl : 02 ram paging (sram) registers (page 39 ) x,6ch tmp_dr0 data[7:0] rw : 00 x,6dh tmp_dr1 data[7:0] rw : 00 x,6eh tmp_dr2 data[7:0] rw : 00 x,6fh tmp_dr3 data[7:0] rw : 00 0,d0h cur_pp page bits[2:0] rw : 0 0,d1h stk_pp page bits[2:0] rw : 0 0,d3h idx_pp page bits[2:0] rw : 0 0,d4h mvr_pp page bits[2:0] rw : 0 0,d5h mvw_pp page bits[2:0] rw : 0 interrupt controller registers (page 45 ) 0,dah int_clr0 i2c sleep spi gpio timer0 truetouch analog v monitor rw : 00 0,dbh int_clr1 endpoint3 endpoint2 endpoint1 endpoint0 usb sof usb bus rst timer2 timer1 rw : 00 0,dch int_clr2 usb_wake endpoint8 endpoint7 endpoint6 endpoint5 endpoint4 rw : 00 0,deh int_msk2 usb wakeup endpoint8 endpoint7 endpoint6 endpoint5 endpoint4 rw : 00 0,dfh int_msk1 endpoint3 endpoint2 endpoint1 endpoint0 usb sof usb bus reset timer2 timer1 rw : 00 0,e0h int_msk0 i2c sleep spi gpio timer0 truetouch analog v monitor rw : 00 0,e1h int_sw_en enswint rw : 0 0,e2h int_vc pending interrupt[7:0] rc : 00 general purpose i/o (gpio) registers (page 59 ) 0,00h prt0dr data[7:0] rw : 00 0,01h prt0ie interrupt enables[7:0] rw : 00 0,04h prt1dr data[7:0] rw : 00 0,05h prt1ie interrupt enables[7:0] rw : 00 0,08h prt2dr data[7:0] rw : 00 0,09h prt2ie interrupt enables[7:0] rw : 00 0,0ch prt3dr data[7:0] rw : 00 0,0dh prt3ie interrupt enables[7:0] rw : 00 1,00h prt0dm0 drive mode 0[7:0] rw : 00 1,01h prt0dm1 drive mode 1[7:0] rw : ff 1,04h prt1dm0 drive mode 0[7:0] rw : 00 1,05h prt1dm1 drive mode 1[7:0] rw : ff 1,08h prt2dm0 drive mode 0[7:0] rw : 00 1,09h prt2dm1 drive mode 1[7:0] rw : ff 1,0ch prt3dm0 drive mode 0[7:0] rw : 00 1,0dh prt3dm1 drive mode 1[7:0] rw : ff 0,10h prtxdr data[7:0] rw : 00 0,11h prtxie interrupt enables[7:0] rw : 00 1,10h prtxdm0 drive mode 0[7:0] rw : 00 1,11h prtxdm1 drive mode 0[7:0] rw : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 25 section b: psoc core 1,dch io_cfg1 strongp range[1:0] p1_low_ thrs spiclk_on _p10 reg_en ioint rw : 00 internal main oscillator (imo) register (page 64 ) 1,e8h imo_tr trim[7:0] w: 00 1,fah imo_tr1 fine trim[2:0] rw : 00 x,feh cpu_scr1 iress slim[1:o] iramdis # : 00 1,e2h osc_cr2 clk48men extclken imodis rw : 00 internal low speed oscillator (ilo) register (page 68 ) 1,e9h ilo_tr pd_mode ilofreq satbiasb freq trim[3:0] rw : 18 external crystal oscillator (eco) registers (page 69 ) 1,d2h eco_enbus eco_enbus[2:0] rw : 07 1,d3h eco_trim eco_xgm[2:0] eco_pl[1:0] rw : 00 1,e1h eco_cfg eco_lpm eco_exw eco_ex rw : 00 sleep and watchdog registers (page 77 ) 0,e3h res_wdt wdsl_clear[7:0] w : 00 1,ebh slp_cfg pssdc[1:0] rw : 0 1,ech slp_cfg2 alt_buzz [1:0] i2c_on lso_off rw : 00 1,edh slp_cfg3 dbl_taps t2tap [1:0] t1tap [1:0] t0tap [1:0] rw : 0x7f legend l the and f, expr; or f, expr; and xor f, expr in structions can be used to modify this register. x an ?x? before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. c clearable register or bit(s). r read register or bit(s). w write register or bit(s). summary table of the core registers (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access [+] feedback
26 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section b: psoc core [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 27 2. cpu core (m8c) this chapter explains the cpu core, called the m8c, and its asso ciated register. it covers the in ternal m8c registers, address spaces, instruction set and formats. for additional information conc erning the m8c instruction set, refer to the psoc designer assembly language user guide available at the cypress web site ( http://www.cypress.com ). for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 2.1 overview the m8c is a four mips 8-bit harvard architecture micropro- cessor. selectable processor clock speeds up to 24 mhz enable you to tune the m8c to a particular application?s per- formance and power requirements. the m8c supports a rich instruction set that allows for efficient low-level language support. 2.2 internal registers the m8c has five internal registers that are used in program execution. here is a li st of these registers. accumulator (a) index (x) program counter (pc) stack pointer (sp) flags (f) all the internal m8c registers are 8 bits in width, except for the pc which is 16 bits wide. upon reset , a, x, pc, and sp are reset to 00h. the flag register (f) is reset to 02h, indi- cating that the z flag is set . with each stack operation, the sp is automatically incre- mented or decremented so that it always points to the next stack byte in ram. if the last byte in the stack is at address ffh , the stack pointer wraps to ram address 00h. it is the firmware developer?s responsibility to ensure that the stack does not overlap with user defined variables in ram. with the exception of the f re gister, the m8c internal regis- ters are not accessible via an explicit register address. the internal m8c registers are accessed using these instruc- tions: mov a, expr mov x, expr swap a, sp or f, expr jmp label the f register is read by using address f7h in either register bank. 2.3 address spaces the m8c has three address spaces: rom , ram , and regis- ters. the rom address space includes the supervisory rom (srom) and the flash. the rom address space is accessed through its own address and data bus . the rom address space is composed of the supervisory rom and the on-chip flash program store. flash is orga- nized into 128-byte blocks. program store page boundaries are not an issue because the m8c automatically increments the 16-bit pc on every instruction. this makes the block boundaries invisible to user code. instructions occurring on a 128-byte flash page boundar y (with the exception of jmp instructions) incur an extra m8c clock cycle, since the upper byte of the pc is incremented. the register address space is used to configure the psoc microcontroller?s pr ogrammable blocks. it consists of two banks of 256 bytes each. to switch between banks, the xio bit in the flag register is set or cleared (set for bank1, cleared for bank0). the common convention is to leave the bank set to bank0 (xio cleared), switch to bank1 as needed (set xio), then switch back to bank0. [+] feedback
28 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cpu core (m8c) 2.4 instruction set summary the instruction set is summarized in both ta b l e 2 - 1 and ta b l e 2 - 2 (in numeric and mnemonic order, respectively), and serves as a quick reference. if more information is needed, the instruction set summary tables are described in detail in the psoc designer assembly language user guide (refer to the http://www.cypress.com web site). table 2-1. instruction set summary sorted numerically by opcode opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags 00 15 1 ssc 2d 8 2 or [x+expr], a z 5a 5 2 mov [expr], x 01 4 2 add a, expr c, z 2e 9 3 or [expr], expr z 5b 4 1 mov a, x z 02 6 2 add a, [expr] c, z 2f 10 3 or [x+expr], expr z 5c 4 1 mov x, a 03 7 2 add a, [x+expr] c, z 30 9 1 halt 5d 6 2 mov a, reg[expr] z 04 7 2 add [expr], a c, z 31 4 2 xor a, expr z 5e 7 2 mov a, reg[x+expr] z 05 8 2 add [x+expr], a c, z 32 6 2 xor a, [expr] z 5f 10 3 mov [expr], [expr] 06 9 3 add [expr], expr c, z 33 7 2 xor a, [x+expr] z 60 5 2 mov reg[expr], a 07 10 3 add [x+expr], expr c, z 34 7 2 xor [expr], a z 61 6 2 mov reg[x+expr], a 08 4 1 push a 35 8 2 xor [x+expr], a z 62 8 3 mov reg[expr], expr 09 4 2 adc a, expr c, z 36 9 3 xor [expr], expr z 63 9 3 mov reg[x+expr], expr 0a 6 2 adc a, [expr] c, z 37 10 3 xor [x+expr], expr z 64 4 1 asl a c, z 0b 7 2 adc a, [x+expr] c, z 38 5 2 add sp, expr 65 7 2 asl [expr] c, z 0c 7 2 adc [expr], a c, z 39 5 2 cmp a, expr if (a=b) z=1 if (a psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 29 cpu core (m8c) table 2-2. instruction set summary sorted alphabetically by mnemonic opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags 09 4 2 adc a, expr c, z 76 7 2 inc [expr] c, z 20 5 1 pop x 0a 6 2 adc a, [expr] c, z 77 8 2 inc [x+expr] c, z 18 5 1 pop a z 0b 7 2 adc a, [x+expr] c, z fx 13 2 index z 10 4 1 push x 0c 7 2 adc [expr], a c, z ex 7 2 jacc 08 4 1 push a 0d 8 2 adc [x+expr], a c, z cx 5 2 jc 7e 10 1 reti c, z 0e 9 3 adc [expr], expr c, z 8x 5 2 jmp 7f 8 1 ret 0f 10 3 adc [x+expr], expr c, z dx 5 2 jnc 6a 4 1 rlc a c, z 01 4 2 add a, expr c, z bx 5 2 jnz 6b 7 2 rlc [expr] c, z 02 6 2 add a, [expr] c, z ax 5 2 jz 6c 8 2 rlc [x+expr] c, z 03 7 2 add a, [x+expr] c, z 7c 13 3 lcall 28 11 1 romx z 04 7 2 add [expr], a c, z 7d 7 3 ljmp 6d 4 1 rrc a c, z 05 8 2 add [x+expr], a c, z 4f 4 1 mov x, sp 6e 7 2 rrc [expr] c, z 06 9 3 add [expr], expr c, z 50 4 2 mov a, expr z 6f 8 2 rrc [x+expr] c, z 07 10 3 add [x+expr], expr c, z 51 5 2 mov a, [expr] z 19 4 2 sbb a, expr c, z 38 5 2 add sp, expr 52 6 2 mov a, [x+expr] z 1a 6 2 sbb a, [expr] c, z 21 4 2 and a, expr z 53 5 2 mov [expr], a 1b 7 2 sbb a, [x+expr] c, z 22 6 2 and a, [expr] z 54 6 2 mov [x+expr], a 1c 7 2 sbb [expr], a c, z 23 7 2 and a, [x+expr] z 55 8 3 mov [expr], expr 1d 8 2 sbb [x+expr], a c, z 24 7 2 and [expr], a z 56 9 3 mov [x+expr], expr 1e 9 3 sbb [expr], expr c, z 25 8 2 and [x+expr], a z 57 4 2 mov x, expr 1f 10 3 sbb [x+expr], expr c, z 26 9 3 and [expr], expr z 58 6 2 mov x, [expr] 00 15 1 ssc 27 10 3 and [x+expr], expr z 59 7 2 mov x, [x+expr] 11 4 2 sub a, expr c, z 70 4 2 and f, expr c, z 5a 5 2 mov [expr], x 12 6 2 sub a, [expr] c, z 41 9 3 and reg[expr], expr z 5b 4 1 mov a, x z 13 7 2 sub a, [x+expr] c, z 42 10 3 and reg[x+expr], expr z 5c 4 1 mov x, a 14 7 2 sub [expr], a c, z 64 4 1 asl a c, z 5d 6 2 mov a, reg[expr] z 15 8 2 sub [x+expr], a c, z 65 7 2 asl [expr] c, z 5e 7 2 mov a, reg[x+expr] z 16 9 3 sub [expr], expr c, z 66 8 2 asl [x+expr] c, z 5f 10 3 mov [expr], [expr] 17 10 3 sub [x+expr], expr c, z 67 4 1 asr a c, z 60 5 2 mov reg[expr], a 4b 5 1 swap a, x z 68 7 2 asr [expr] c, z 61 6 2 mov reg[x+expr], a 4c 7 2 swap a, [expr] z 69 8 2 asr [x+expr] c, z 62 8 3 mov reg[expr], expr 4d 7 2 swap x, [expr] 9x 11 2 call 63 9 3 mov reg[x+expr], expr 4e 5 1 swap a, sp z 39 5 2 cmp a, expr if (a=b) z=1 if (a 30 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cpu core (m8c) 2.5 instruction formats the m8c has a total of seven instruction formats that use instruction lengths of one, two, and three bytes. all instruc- tion bytes are taken from the program memory (flash), using an address and data bus that are independent from the address and data buses used for register and ram access. while examples of instructions are given in this section, refer to the psoc designer assembly language user guide for detailed information on individual instructions. 2.5.1 one-byte instructions many instructions, such as so me of the mov instructions, have single-byte forms because they do not use an address or data as an operand. as shown in ta b l e 2 - 3 , one-byte instructions use an 8-bit opcode. the set of one-byte instructions are divided into four categories, according to where their results are stored. the first category of one-byte instructions are those that do not update any registers or ram. only the one-byte nop and ssc instructions fit this category. while the program counter is incremented as these instructions execute, they do not cause any other internal m8c registers to update, nor do these instructions directly af fect the register space or the ram address space. the ssc instruction causes srom code to run, which modifies ram and the m8c internal reg- isters. the second category contains the two push instructions. the push instructions are unique because they are the only one-byte instructions that modify a ram address. these instructions automatical ly increment the sp. the third category contains the halt instruction. the halt instruction is unique because it is the only one-byte instruc- tion that modifies a user register. the halt instruction mod- ifies user register space address ffh (cpu_scr0 register). the final category for one-byte instructions are those that update the internal m8c regist ers. this category holds the largest number of instructions: asl , asr , cpl , dec , inc , mov , pop , ret , reti , rlc , romx , rrc , swap . these instructions cause the a, x, and sp registers or sram to update. 2.5.2 two-byte instructions the majority of m8c instruct ions are two bytes in length. while these instructions are divided into categories identical to the one-byte instructions, this does not provide a useful distinction between the three two-byte instruction formats that the m8c uses. the first two-byte instruction format, shown in the first row of ta b l e 2 - 4 , is used by short jumps and calls: call , jmp , jacc , index , jc , jnc , jnz , jz . this instruction format uses only 4 bits for the instruction opcode, leaving 12 bits to store the relative destination address in a two?s-complement form. these instructions can change program execution to an address relative to the current address by -2048 or +2047. the second two-byte instruction format, shown in the sec- ond row of ta b l e 2 - 4 , is used by instructions that employ the source immediate addressing mode (see the psoc designer assembly language user guide ). the destination for these instructions is an internal m8c register, while the source is a constant value. an example of this type of instruction is add a, 7 . the third two-byte instruction format, shown in the third row of ta b l e 2 - 4 , is used by a wide range of instructions and addressing modes. the following is a list of the addressing modes that use this third two-byte instruction format: source direct ( add a, [7] ) source indexed ( add a, [x+7] ) destination direct ( add [7], a ) destination indexed ( add [x+7], a ) source indirect post increment ( mvi a, [7] ) destination indirect post increment ( mvi [7], a ) for more information on addressing modes see the psoc designer assembly language user guide . table 2-3. one-byte instruction format byte 0 8-bit opcode table 2-4. two-byte instruction formats byte 0 byte 1 4-bit opcode 12-bit relative address 8-bit opcode 8-bit data 8-bit opcode 8-bit address [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 31 cpu core (m8c) 2.5.3 three-byte instructions the three-byte instruction formats are the second most prevalent instruction formats. these instructions need three bytes because they either move data between two addresses in the user accessible address space (registers and ram) or they hold 16-bit absolute addresses as the destination of a long jump or long call. the first instruction format, shown in the first row of table 2-5 , is used by the ljmp and lcall instructions. these instructions change pr ogram execution uncondition- ally to an absolute address. the instructions use an 8-bit opcode, leaving room for a 16-bit destination address. the second three-byte instruction format, shown in the sec- ond row of ta b l e 2 - 5 , is used by the following two address- ing modes: destination direct source immediate ( add [7], 5 ) destination indexed source immediate ( add [x+7], 5 ) the third three-byte instruction format, shown in the third row of ta b l e 2 - 5 , is for the destination direct source direct addressing mode, which is used by only one instruction. this instruction format uses an 8-bit opcode followed by two 8-bit addresses. the first address is the destination address in ram, while the second address is the source address in ram. the following is an example of this instruction: mov [7], [5] table 2-5. three-byte instruction formats byte 0 byte 1 byte 2 8-bit opcode 16-bit address (msb, lsb) 8-bit opcode 8-bit address 8-bit data 8-bit opcode 8-bit address 8-bit address [+] feedback
32 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cpu core (m8c) 2.6 register definitions the following register is associated with the cpu core (m8c). the register description has an associated register table show- ing the bit structure. the bits that are grayed out in the table are reserved bi ts and are not detailed in the register descrip tion that follows. always write reserved bits with a value of ?0?. 2.6.1 cpu_f register the m8c flag register (cpu_f) provides read access to the m8c flags. bits 7 and 6: pgmode[1:0]. pgmode determines how the cur_pp, stk_pp, and idx_pp registers are used in form- ing effective ram addresses for direct address mode and indexed address mode operands. pgmode also determines whether the stack page is determined by the stk_pp or idx_pp register. (see the register definitions on page 42 in the ram paging chapter.) bit 4: xio. the i/o bank select bit, also known as the regis- ter bank select bit, is used to select the register bank that is active for a register read or write. this bit allows the psoc device to have 512 8-bit registers and is thought of as the ninth address bit for registers. the address space accessed when the xio bit is set to ?0? is called user space , while address space accessed when the xio bit is set to ?1? is called configuration space . bit 2: carry. the carry flag bit is set or cleared in response to the result of several instructions. it is also manipulated by the flag logic opcodes (for ex ample, or f, 4). see the psoc designer assembly language user guide for more details. bit 1: zero. the zero flag bit is set or cleared in response to the result of seve ral instructions. it is also manipulated by the flag logic opcodes (for ex ample, or f, 2). see the psoc designer assembly language user guide for more details. bit 0: gie. the state of the global interrupt enable bit determines whether interrupt s (by way of the interrupt request (irq)) are recognized by the m8c. this bit is set or cleared using the flag logic instructions (for example, or f, 1). gie is also automatically cleared when an interrupt is processed, after the flag byte has been stored on the stack, preventing nested interrupts. if wanted, set the bit in an interrupt service routine (isr) . for gie=1, the m8c sam- ples the irq input for each in struction. for gie=0, the m8c ignores the irq. for additional information, refer to the cpu_f register on page 254 . 2.6.2 related registers the following registers are related to the m8c block: cpu_scr1 register on page 257 . cpu_scr0 register on page 258 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access x,f7h cpu_f pgmode[1:0] xio carry zero gie rl : 02 legend l the and f, expr; or f, expr; and xor f, expr flag instructions can be used to modify this register. x an ?x? before the comma in the address field indicates that this register can be read or written to no matter what bank is use d. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 33 3. supervisory rom (srom) this chapter discusses the supervisory ro m (srom) functions. for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 3.1 architectural description the srom holds code that boots a psoc device, calibrates circuitry, and performs flash operations. the functions pro- vided by the srom are called from code stored in the flash or by device programmers. the srom is used to boot the part and provide interface functions to the flash blocks. ( table 3-1 lists the srom functions.) the srom function s are accessed by executing the supervisory system call instruction ( ssc ), which has an opcode of 00h. before executing the ssc , the m8c's accu- mulator needs to load with the wanted srom function code from ta b l e 3 - 1 . attempting to access undefined functions (reserved func- tions) causes a halt . the srom functions execute code with calls; therefore, the functions require stack space. with the exception of reset, all of the srom functions have a parameter block in sram that you must configure before executing the ssc . table 3-2 lists all possible parameter block variables. the meaning of each parameter, with regards to a specific srom function, is described later in this chapter. because the ssc instruction clears the cpu_f pgmode bits, all parameter block variable addresses are in sram page 0. the cpu_f value is automatically restored at the end of the srom function. the mvr_pp and the mvw_pp pointers are not disabled by clearing the cpu_f pgmode bits. therefore, the pointer parameter is interp reted as an address in the page indicated by the mvi page pointers, when the supervi- sory operation is called. this allows the data buffer used in the supervisory operation to be located in any sram page. (see the ram paging chapter on page 39 for more details regarding the mvr_pp and mvw_pp pointers.) note protectblock and eraseall (described on page 36 ) srom functions are not listed in the table above because they are dependent on external pro- gramming. note clock and delay are ignored and are reserved for future use. two important variables that are used for all functions are key1 and key2. these variables are used to help discrimi- nate between valid sscs and inadvertent sscs . key1 must always have a value of 3ah, while key2 must have the same value as the stack pointer when the srom function begins execution. this is the sp (stack pointer) value when the ssc opcode is executed, plus three. for all srom func- tions except swbootreset, if either of the keys do not match the expected values, the m8c halts. the swbootre- set function does not check the key values. it only checks to see if the accumulator's value is 0x00. table 3-1. list of srom functions function code function name required stack space page 00h swbootreset 0 34 01h readblock 7 35 02h writeblock 7 35 03h eraseblock 5 36 06h tableread 3 36 07h checksum 4 37 08h calibrate0 4 37 09h calibrate1 3 37 0ah writeandverify 7 37 0fh hwbootreset 3 38 table 3-2. srom function variables variable name sram address key1/return code 0,f8h key2 0,f9h blockid 0,fah pointer 0,fbh clock 0,fch reserved 0,fdh delay 0,feh reserved 0,ffh [+] feedback
34 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c supervisory rom (srom) the following code example put s the correct value in key1 and key2. the code is preceded by a halt , to force the program to jump directly into the setup code and not acci- dentally run into it. 1. halt 2. sscop: mov [key1], 3ah 3. mov x, sp 4. mov a, x 5. add a, 3 6. mov [key2], a 3.1.1 additional srom feature return codes: these aid in the determination of success or failure of a particular functi on. the return code is stored in key1?s position in the parame ter block. the checksum and tableread functions do not have return codes because key1?s position in the parameter block is used to return other data. note read, write, and erase operat ions may fail if the target block is read or write protecte d. block protection levels are set during device programming and cannot be modified from code in the psoc device. 3.1.2 srom function descriptions 3.1.2.1 swbootreset function the srom function swbootreset is responsible for transi- tioning the device from a reset state to running user code. see chapter ?system resets? on page 135 for more infor- mation on what events causes the swbootreset function to execute. the swbootreset function executes whenever the srom is entered with an m8c accumulator value of 00h; the sram parameter block is not used as an input to the function. this happens, by design, after a hardware reset because the m8c's accumulator is reset to 00h or when user code exe- cutes the ssc instruction with an accumulator value of 00h. if the checksum of the cali bration data is valid, the swbootreset function ends by setting the internal m8c reg- isters (cpu_sp, cpu_pc, cpu_x, cpu_f, cpu_a) to 00h, writing 00h to most sram addresses in sram page 0, and then begins to execute user code at address 0000h. (see table 3-5 and the following paragraphs for more information on which sram addresses are modified.) if the checksum is not valid, an internal reset is executed and the boot process starts over. if this condition occurs, the internal reset status bit (iress) is set in the cpu_scr1 register. in devices with more than 256 bytes of sram, no sram is modified by the swbootreset function in sram pages numbered higher than '0'. ta b l e 3 - 5 documents the value of all the sram addresses in page 0 after a successful swbootreset. a value of "xx" indicates that the sram address is not modified by the swbootreset function. a hex value indicates that the address always has the indica ted value after a successful swbootreset. a "??" indicates that the value, after a swbootreset, is determined by the value of the iramdis bit in the cpu_scr1 register. if iramdis is not set, these addresses are initialized to 00h. if iramdis is set, these addresses are not modified by a swbootreset after a watchdog reset. table 3-3. srom return code meanings return code value description 00h success. 01h function not allowed because of block level protection. 02h software reset without hardware reset. 03h fatal error, srom halted. 04h write and verify error. 06h failure of smartwrite parameters checksum [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 35 supervisory rom (srom) the iramdis bit allows the preservation of variables even if a watchdog reset (wdr) occurs. the iramdis bit is reset by all system resets except wa tchdog reset. therefore, this bit is only useful for watchdog resets and not general resets. address f8h is the return code byte for all srom functions (except checksum and tableread); for this function, the only acceptable values are 00h, 02h, and 06h. address fch is the fail count variable. after por (power on reset), wdr, or xres (external reset), the variable is initialized to 00h by the srom. each time the checksum fails, the fail count is incremented. therefor e, if it takes two passes through swbootreset to get a good checksum, the fail count is 01h. 3.1.2.2 readblock function the readblock function is used to read 128 contiguous bytes from flash: a block. the device has 32 kb of flash and has two hundred fifty-six 128-byte blocks. valid block ids are 0x00 to 0xff. the first thing the readblock function does is check the pro- tection bits to determine if the wanted blockid is readable. if read protection is turned on, the readblock function exits setting the accumula tor and key2 back to 00h. key1 has a value of 01h indicating a read failure. if read protection is not e nabled, the function reads 128 bytes from the flash using a romx instruction and stores the results in sram using an mvi instruction. the 128 bytes are stored in sram, beginning at the address indicated by the value of the pointer parameter. when the readblock completes successfully, the accumulator, key1, and key2 has a value of 00h. note an mvi [expr], a stores the flash block contents in sram meaning that you can use the mvw_pp register to indicate which sram pages receive the data. 3.1.2.3 writeblock function the writeblock function stores data in the flash. no verifi- cation of the data is performe d, but execution time is about 1 ms less than the writeandverify function. the writeand- verify function is the recommended method for altering the data in one block of flash ( see ?writeandverify function? on page 37 ). data moves 128 bytes at a time from sram to flash. this is a two-step process, the first step is to load the page latch with 128 bytes of data and it is followed by the programming of the corresponding block of flash. no erase is needed before writeblock. if write protection is turned on, then the writeblock function exits, setting the accumulator and key2 back to 00h. key1 has a value of 01h, indicating a write failure. write protection is set when the psoc device is programmed externally and cannot be changed through the ssc function. the blockid of the flash blo ck, where the data is stored, must be determined and stored at sram address fah. valid block ids are 0x00 to 0xff. table 3-5. sram map post swbootreset (00h) address 0 1 2 3 4 5 6 7 8 9 a b c d e f 0x0_ 0x00 0x00 0x00 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x1_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x2_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x3_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x4_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x5_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x6_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x7_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x8_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x9_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0xa_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0xb_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0xc_ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0xd_ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xe_ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xf_ 0x00 0x00 0x00 0x00 0x00 0x00 ?? ?? 0x00 0x02 0x06 xx 0x00 0x00 0xn xx 0x00 0x00 table 3-6. flash memory organization psoc device amount of flash amount of sram number of blocks per bank number of banks cy8ctmg200, cy8ctst200 32 kb 2k bytes 256 1 table 3-7. readblock parameters (01h) name address type description mvw_pp 0,d5h register mvi write page pointer register. key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. blockid 0,fah ram flash block number. pointer 0,fbh ram addresses in sram to store returned data. [+] feedback
36 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c supervisory rom (srom) an mvi a, [expr] instruction is used to move data from sram into flash. therefore, use the mvi read pointer (mvr_pp register) to specify which sram page from which data is pulled. using the mvi read pointer and the parameter blocks pointer value allows the srom writeblock func- tion to move data from any sram page into any flash block. the sram address, the first of the 128 bytes to store in flash, is indicated using the pointer variable in the parameter block (sram address fbh). 3.1.2.4 eraseblock function the eraseblock function is not recommended for use. the functionality is redundant with the writeblock and writeand- verify functions. the only practical use is for clearing all data in a 128 byte block of contigu ous bytes in flash to 0x00. if used, it should not be called repeatedly on the same block. it may be used between writeandverify or writeblock opera- tions. if write protection is turned on, then the eraseblock function exits, setting the accumulator and key2 back to 00h. key1 has a value of 01h, indicating a write failure. to set up the parameter block for the eraseblock function, store the correct key values in key1 and key2. the block number to erase must be stored in the blockid variable. 3.1.2.5 protectblock function the psoc devices offer flash protection on a block-by- block basis. ta b l e 3 - 1 0 lists the protection modes available. in the table, er and ew indicate the ability to perform exter- nal reads and writes (that is, by an external programmer). for internal writes, iw is used. internal reading is always permitted by way of the romx instruction. an sr indicates the ability to read by way of the srom readblock function. in this table, note that all pr otection is removed by eraseall. 3.1.2.6 tableread function the tableread function gives the user access to part-spe- cific data stored in the flash during manufacturing. the flash for these tables is separate from the program flash and is not directly accessible. it also returns a revision id for the die (do not confus e this with the silicon id stored in the table 0 row in table 3-14 ). there are four 8-byte t ables in the cy8ctmg20x, cy8ctst200 devices. 3.1.2.7 eraseall function the eraseall function performs a series of steps that destroys the user data in the flash banks and resets the protection block in each flash bank to all zeros (the unpro- tected state). this function is only executed by an external programmer. if eraseall is executed from code, the m8c halts without touching the flash or protections. see table 3-13 . the three other hidden bl ocks above the protection block, in each flash bank, are not affected by the eraseall. table 3-8. writeblock parameters (02h) name address type description mvr_pp 0,d4h register mvi read page pointer register. key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. blockid 0,fah ram flash block number. pointer 0,fbh ram first of 128 addresses in sram, where the data to be stored in flash, is located before calling writeblock. table 3-9. eraseblock parameters (03h) name address type description key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. blockid 0,fah ram flash block number. table 3-10. protect block modes mode settings description in psoc designer 00b sr er ew iw unprotected u = unprotected 01b sr er ew iw read protect f = factory upgrade 10b sr er ew iw disable external write r = field upgrade 11b sr er ew iw disable internal write w = full protection table 3-11. protection level bit packing 7 6 5 4 3 2 1 0 block n+3 block n+2 block n+1 block n table 3-12. tableread parameters (06h) name address type description key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. blockid 0,fah ram table number to read. table 3-13. eraseall parameters (05h) name address type description key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 37 supervisory rom (srom) 3.1.2.8 checksum function the checksum function calculates a 16-bit checksum over a user specifiable nu mber of blocks, wi thin a single flash bank starting at block zero. the blockid parameter is used to pass in the numbe r of blocks to checksum. a blockid value of '1' calculates the checksum of only block 0, while a blockid value of '0' calculates the checksum of the entire flash bank. the 16-bit checksum is returned in key1 and key2. the parameter key1 holds the lower 8 bits of the checksum and the parameter key2 holds the u pper 8 bits of the checksum. 3.1.2.9 calibrate0 function this function may be executed at any time to set all calibra- tion values. however, it is unnecessary to call this function. this function is simply documented for completeness. the calibration values are accessed by way of the tableread function, which is described in the section titled tableread function, on page 36 . 3.1.2.10 calibrate1 function while the calibrate1 function is a completely separate func- tion from calibrate0, they perform the same task, which is to transfer the calibration values stored in a special area of flash to their appropriate regi sters. what is unique about calibrate1 is that it calculat es a checksum of the calibration data and, if that checksum is determined as invalid, calibrate1 causes a hardware reset by generating an inter- nal reset. if this occurs, it is indicated by setting the internal reset status bit (iress) in the cpu_scr1 register. the calibrate1 function uses sram to calculate a check- sum of the calibration data. the pointer value is used to indicate the address of a 38-byte buffer used by this func- tion. when the function completes, the 38 bytes are set to 00h. an mvi a, [expr] and an mvi [expr], a instruction are used to move data between sram and flash. there- fore, the mvi write pointer (mvw_pp) and the mvi read pointer (mvr_pp) must be specified to the same sram page to control the page of ram used for the operations. calibrate1 was created as a sub-function of swbootreset and the calibrate1 function code was added to provide direct access. for more in formation on how calibrate1 works, see swbootreset function on page 34 . this function may be executed at any time to reset all cali- bration values. however, it is unnecessary to call this func- tion. this function is simply documented for completeness. the calibration values are accessed by way of the tableread function, which is described in the section titled tableread function on page 36 . 3.1.2.11 writeandverify function writeandverify is the recommend function for modifying one block of data in flash. the writeandverify function works exactly the same as the writeblock function except that the flash data is verified after the write. the execution time is table 3-14. flash tables with assigned values table 0 silicon id low byte reserved table 0 silicon id high byte expected numbers = # bits used to encode = max values (including 0) = bits targeted = reserved table 1 imo 6 mhz trim imo 12 mhz trim imo 24 mhz trim imo 24 mhz usb trim (high power) reserved table 2 reserved table 3 reserved table 3-15. checksu m parameters (07h) name address type description key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. blockid 0,fah ram number of flash blocks from which to calculate the checksum. table 3-16. calibrate0 parameters (08h) name address type description key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. table 3-17. calibrate1 parameters (09h) name address type description key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. pointer 0,fbh ram first of 30 sram addresses used by this function. mvr_pp 0,d4h register mvi write page pointer. mvw_pp 0,d5h register mvi read page pointer. [+] feedback
38 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c supervisory rom (srom) about 1 ms longer than writeblock (but still within the twrite spec). the function performs a three-step process. in the first step, 128 bytes of data are moved from sram to the flash. in the second step, flash is programmed with the data. in the final step the flash data are compared against the input data values, thus verifying that the write was suc- cessful. the write and verify is one srom operation; there- fore, the srom is not exited until the verify is completed. the parameters for this block are identical to the writeblock (see writeblock function on page 35 ). if the verify operation fails, the 0x04 error code is returned at sram address 0xf8 3.1.2.12 hwbootreset function the hwbootreset function is used to force a hardware reset. a hardware reset caus es all registers to go back to their por state. then, the srom swbootreset function executes, followed by flash code execution beginning at address 0x0000. the hwbootreset function only requires that the cpu_a, key1, and key2 be set up correctly. as with all other srom functions, if the setu p is incorrect, the srom exe- cutes a halt . then, either a por, xres, or wdr is needed to clear the halt . see chapter ?system resets? on page 135 for more information. 3.2 register definitions this chapter has no register detail information because there are no registers directly assigned to the supervisory rom. table 3-18. writeandverify parameters (0ah) name address type description key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. blockid 0,fah ram flash block number. pointer 0,fbh ram first of 128 addresses in sram, where the data to be stored in flash, is located before calling writeblock. table 3-19. hwbootreset parameters (0fh) name address type description key1 0,f8h ram 3ah. key2 0,f9h ram stack pointer value+3, when ssc is executed. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 4. ram paging this chapter explains the psoc device?s use of ram paging and its associated registers. for a complete table of the ram paging registers, refer to the summary table of the core registers on page 24 . for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 4.1 architectural description the m8c is an 8-bit cpu with an 8-bit memory address bus. the memory address bus allows the m8c to access up to 256 bytes of sram, to increase the amount of available sram and preserve the m8c assembly language. the psoc device has 1k and 2k bytes of sram with eight pages of memory architecture. to take full advantage of the paged memory architecture of the psoc device, you use several registers and manage two cpu_f register bits. however, the power on reset (por) value for all of the paging registers and cpu_f bits is zero. this places the psoc device in a mode identical to devices with only 256 bytes of sram. there is no need to understand all of the paging registers to take advantage of the additional sram available in some devices. to use the additional sram pages you modify the memory paging logic reset state. the memory paging architectu re consists of five areas: stack operations interrupts mvi instructions current page pointer indexed memory page pointer the first three of these areas do not depend upon the cpu_f register's pgmode bits and are covered in the next subsections after basic paging. the function of the last two depend upon the cpu_f pgmode bits and are covered last. 4.1.1 basic paging to increase the amount of sram, the m8c accesses mem- ory page bits. the memory page bits are located in the cur_pp register and allow for selection of one of eight sram pages. in addition to setting the page bits, page mode is enabled by setting the cpu_f[7] bit. if page mode is not enabled, the page bits are ignored and all non-stack memory access is di rected to page 0. after page mode is enabled and the page bits are set, all instructions that operate on memory access the sram page indicated by the page bits. the exceptions to this are the instructions that operate on the stack and the mvi instruc- tions: push , pop , lcall , reti , ret , call , and mvi . see the description of stack operations and mvi instructions below for a more detailed discussion. figure 4-1. data memory organization page 0 sram 256 bytes isr page 6 sram 256 bytes page 5 sram 256 bytes page 3 sram 256 bytes page 2 sram 256 bytes page 1 sram 256 bytes page 7 sram 256 bytes page 4 sram 256 bytes 00h ffh [+] feedback
40 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c ram paging 4.1.2 stack operations as mentioned previously, the paging architecture's reset state puts the in a mode identical to that of a 256-byte device. therefore, upon reset, all memory accesses are to page 0. the sram page that stack operations use is deter- mined by the value of the three least significant bits (lsb) of the stack page pointer register (stk_pp). stack operations have no dependency on the pgmode bits in the cpu_f reg- ister. stack operations are those that use the stack pointer (sp) to calculate their affected address. refer to the psoc designer assembly language user guide for more informa- tion on all m8c instructions. stack memory accesses are a spec ial case. if they were not, the stack could fragment across several pages. to prevent the stack from fragmenting, al l instructions that operate on the stack automatically use the page indicated by the stk_pp register. therefore, if the program encounters a call, the psoc device automat ically pushes the program counter onto the stack page indicated by stk_pp. after the program counter is pushed, the sram paging mode auto- matically switches back to the precall mode. all other stack operations, such as ret and pop , follow the same rule as call . the stack is confined to a single sram page and the stack pointer wraps from 00h to ffh and ffh to 00h. the user code must ensure that the stack is not damaged because of stack wrapping. because the value of the stk_pp register can change at any time, it is theo retically possible to manage the stack in such a way as to allow it to grow beyond one sram page or manage multiple stacks. howeve r, the only supported use of the stk_pp register is when its value is set before the first stack operation and not changed again. 4.1.3 interrupts interrupts, in a multipage sram psoc device, operate the same as interrupts in a 256-byte device. however, because the cpu_f register is automatically set to 0x00 on an inter- rupt and because of the nonlinear nature of interrupts in a system, other parts of the memory paging architecture can be affected. interrupts are an abrupt change in program flow. if no spe- cial action is taken on interrupts by the psoc device, the interrupt service routine (isr) could be thrown into any sram page. to prevent this problem, the special address- ing modes for all memory acce sses, except for stack and mvi , are disabled when an isr is entered. the special addressing modes are disabled when the cup_f register is cleared. at the end of the isr, the previous sram address- ing mode is restored when the cpu_f register value is restored by the reti instruction. all interrupt service routine code starts execution in sram page 0. if the isr must change to another sram page, do this by changing the values of the cpu_f[7:6] bits to enable the special sram addressing modes. however, any change made to the cur_pp, idx_pp , or stk_pp registers per- sists after the isr returns. ther efore, have the isr save the current value of any paging register it modifies and restore its value before the isr returns. 4.1.4 mvi instructions mvi instructions use data page pointers of their own (mvr_pp and mvw_pp). this allows a data buffer to be located away from other program variables, but accessible without changing the current page pointer (cur_pp). an mvi instruction performs three memory operations. both forms of the mvi instruction access an address in sram that holds the data pointer (a memory read 1st access), incrementing that value and th en storing it back in sram (a memory write 2nd access). this pointer value must reside in the current page, just as all other nonstack and nonindexed operations on memory. however, the third memory opera- tion uses the mvx_pp register. this third memory access is either a read or a write, depending upon which mvi instruc- tion is used. the mvr_pp pointer is used for the mvi instruction that moves data into the accumulator. the mvw_pp pointer is used for the mvi instruction that moves data from the accumulator into sram. the mvi pointers are always enabled, regardless of the state of the flag register page bits (cpu_f register). 4.1.5 current page pointer the current page pointer determines which sram page is used for all memory accesse s. normal memory accesses are those not covered by other pointers including all non- stack, non- mvi , and nonindexed memory access instruc- tions. the normal memory a ccess instructions have the sram page they operate on determined by the value of the cur_pp register. by default, the cur_pp register has no affect on the sram page that is used for normal memory access, because all normal memory access is forced to sram page 0. the upper bit of the pgmode bits in the cpu_f register determine if the cur_pp register affects normal memory access. when the upper bit of the pgmode bits is set to ?0?, all normal memory access is fo rced to sram page 0. this mode is automatically enabled when an interrupt service routine (isr) is entered. this is because, before the isr is entered, the m8c pushes the current value of the cpu_f register onto the stack and then clears the cpu_f register. therefore, by default, any normal memory access in an isr is guaranteed to occur in sram page 0. when the reti instruction is executed to end the isr, the previous value of the cpu_f register is restored, returning to the previous page mode. th is is the default isr behavior and that it is possible to change the pgmode bits in the cpu_f register while in an isr. if the pgmode bits are changed while in an isr, the pre-isr value is still restored by the reti ; but if the cur_pp register is changed in the [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c ram paging isr, the isr is also required to restore the value before exe- cuting the reti instruction. when the upper bit of the pgmode bits is set to ?1?, all nor- mal memory access is forced to the sram page indicated by the cur_pp register value. table 4-1 summarizes the pgmode bit values and the corresponding memory paging mode. 4.1.6 index memory page pointer the source indexed and destination indexed addressing modes to sram are treated as a unique addressing mode in a psoc device with more than one page of sram. an example of an indexed addressing mode is the mov a, [x+expr] instruction. register access has indexed addressing as well; however, those instructions are not affected by the sram paging architecture. important note int_clr2 if you are not using assembly to program a psoc device, be aware that the compiler writer may restrict the use of some memory paging modes. review the conventions in your compiler?s user guide for more information on restrictio ns or conventions associated with memory paging modes. indexed sram accesses operate in one of three modes: index memory access modes are forced to sram page 0. index memory access modes are directed to the sram page indicated by the value in the stk_pp register. index memory access is forced to the sram page indi- cated by the value in the idx_pp register. the mode is determined by the value of the pgmode bits in the cpu_f register. however, the final sram page that is used also requires setting either the stack page pointer (stk_pp) register or the inde x page pointer (idx_pp) reg- ister. the table below shows the three indexed memory access modes. the third column of the table is provided for reference only. after reset, the pgmode bits are set to 00b. in this mode, index memory accesses are forced to sram page 0, just as they are in a psoc device with only 256 bytes of sram. this mode is also automatically enabled when an interrupt occurs in a psoc device and is considered the default isr mode. this is because before the isr is entered, the m8c pushes the current value of the cpu_f register onto the stack and then clears the cpu_f register. thus, by default, any indexed memory access in an isr is guaranteed to occur in sram page 0. when the reti instruction executes to end the isr, the previous value of the cpu_f register is restored as is the previous page mode. note that this isr behavior is the default and t hat the pgmode bits in the cpu_f register may be changed while in an isr. if the pgmode bits are changed while in an isr, the pre-isr value is still restored by the reti ; but if the stk_pp or idx_pp registers are changed in the isr, the isr is also required to restore the values before executing the reti instruction. the most likely pgmode bit chan ge, while in an isr, is from the default value of 00b to 01b. in the 01b mode, indexed memory access is directed to the sram page indicated by the value of the stk_pp register. by using the pgmode, modification of the stk_pp register value is unnecessary. the stk_pp register determines on which sram page the stack is located. the 01b paging mode is intended to pro- vide easy access to the stack, wh ile in an isr, by setting the cpu_x register (just x in instruction format) equal to value of sp using mov x, sp instruction. the two previous paragraphs covered two of the three indexed memory access modes: stk_pp and forced to sram page 0. note, as shown in ta b l e 4 - 1 , that the stk_pp mode for indexed me mory access is available under two pgmode settings. the 01b mode is intended for isr use and the 11b mode is intended for non-isr use. the third indexed memory access mode requires the pgmode bits to be set to 10b. in this mode indexed memory access is forced to the sram page indicated by the value of the idx_pp register. table 4-1. cpu_f pgmode bit modes cpu_f pgmode bits current sram page indexed sram page typical use 00b 0 0 isr* 01b 0 stk_pp isr with variables on stack 10b cur_pp idx_pp 11b cur_pp stk_pp * mode used by srom functions initiated by the ssc instruction. [+] feedback
42 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c ram paging 4.2 register definitions the following registers are associated with ram paging and are listed in address order. the register descriptions have an associated register table showing the bit st ructure for that register. the bits in t he tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow. alwa ys write reserved bits with a value of ?0?. for a complete t able of ram paging regist ers, refer to the summary table of the core registers on page 24 . 4.2.1 tmp_drx registers the temporary data registers (tmp_dr0, tmp_dr1, tmp_dr2, and tmp_dr3) enhance the performance in multiple sram page psoc devices. these registers have no predefined function (for example, the compiler and hardware do not use these registers) and exist for the user to define. bits 7 to 0: data[7:0]. due to the paged sram architec- ture of psoc devices with more than 256 bytes of sram, a value in sram is not always accessible without first chang- ing the current page. the tmp_drx registers are readable and writable registers that ar e provided to improve the per- formance of multiple sram page psoc devices, by supply- ing some register space for da ta that is always accessible. for an expanded listing of the tmp_drx registers, refer to the summary table of the core registers on page 24 . for additional information, refer to the tmp_drx register on page 266 . 4.2.2 cur_pp register the current page pointer register (cur_pp) sets the effective sram page for normal memory accesses in a multi-sram page psoc device. bits 2 to 0: page bits[2:0]. these bits affect the sram page that is accessed by an instruction when the cpu_f[7:6] bits have a value of either 10b or 11b. source indexed, destination index ed addressing modes, and stack instructions, are never affect ed by the value of the cur_pp register. (see the stk_pp and idx_pp registers for more information.) the source indirect post increment and destination indirect post increment addressing modes, better know as mvi , are only partially affected by the value of the cur_pp register. for mvi instructions, the pointer address is in the sram page indicated by cur_pp, but the address pointed to may be in another sram page. see the mvr_pp and mvw_pp register descriptions for more information. for additional information, refer to the cur_pp register on page 234 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access x,6xh tmp_drx data[7:0] rw : 00 legend x an ?x? before the comma in the address field indicates that this register can be read or written to no matter what bank is use d. an ?x? after the comma in the address field indicates that there are multiple instances of the register. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,d0h cur_pp page bits[2:0] rw : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c ram paging 4.2.3 stk_pp register the stack page pointer register (stk_pp) is used to set the effective sram page for stack memory accesses in a multi-sram page psoc device. bits 2 to 0: page bits[2:0]. these bits have the potential to affect two types of memory access. the purpose of this register is to determine on which sram page to store the stack. in the reset state, this register's value is 0x00 and the stack is in sram page 0. however, if the stk_pp register value is changed, the next stack opera- tion occurs on the sram page indicated by the new stk_pp value. therefore, set the value of this register early in the program and never change it. if the program changes the stk_pp value after the stack grows, the program must ensure that the stk_pp value is restored when needed. note the impact that the stk_pp register has on the stack is independent of the sram paging bits in the cpu_f regis- ter. the second type of memory accesses that the stk_pp reg- ister affects are indexed memory accesses when the cpu_f[7:6] bits are set to 11b. in this mode, source indexed and destination indexed memory accesses are directed to the stack sram page, rather than the sram page indicated by the idx_pp register or sram page 0. for additional information, refer to the stk_pp register on page 235 . 4.2.4 idx_pp register the index page pointer register (idx_pp) sets the effective sram page for indexed memory accesses in a multi-sram page psoc device. bits 2 to 0: page bits[2:0]. these bits allow instructions, which use the source inde xed and destination indexed address modes, to operate on an sram page that is not equal to the current sram page. however, the effect this register has on indexed addressing modes is only enabled when the cpu_f[7:6] is set to 10b. when cpu_f[7:6] is set to 10b and an indexed memory access is made, the access is directed to the sram page indicated by the value of the idx_pp register. see the stk_pp register description for more information on other indexed memory access modes. for additional 4.2.5 mvr_pp register the mvi read page pointer register (mvr_pp) sets the effective sram page for mvi read memory accesses in a multi-sram page psoc device. bits 2 to 0: page bits[2:0]. these bits are only used by the mvi a, [expr] instruction, not to be confused with the mvi [expr], a instruction covered by the mvw_pp reg- ister. this instruction is considered a read because data is transferred from sram to th e microprocessor's a register (cpu_a). when an mvi a, [expr] instruction is executed in a device with more than one page of sram, the sram address that is read by the in struction is determined by the value of the least significant bi ts in this register. however, the pointer for the mvi a, [expr] instruction is always located in the current sram page. see the psoc designer assembly language user guide for more information on the mvi a, [expr] instruction. the function of this register and the mvi instructions are independent of the sram paging bits in the cpu_f register. for additional information, refer to the mvr_pp register on page 237 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,d1h stk_pp page bits[2:0] rw : 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,d3h idx_pp page bits[2:0] rw : 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,d4h mvr_pp page bits[2:0] rw : 0 [+] feedback
44 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c ram paging 4.2.6 mvw_pp register the mvi write page pointer register (mvw_pp) sets the effective sram page for mvi write memory accesses in a multi-sram page psoc device. bits 2 to 0: page bits[2:0]. these bits are only used by the mvi [expr], a instruction, not to be confused with the mvi a, [expr] instruction covered by the mvr_pp regis- ter. this instruction is considered a write because data is transferred from the microprocessor's a register (cpu_a) to sram. when an mvi [expr], a instruction is executed in a device with more than one page of sram, the sram address that is written by the instruction is determined by the value of the least significant bits in this register. however, the pointer for the mvi [expr], a instruction is always located in the current sram page. see the psoc designer assembly language user guide for more information on the mvi [expr], a instruction. the function of this register and the mvi instructions are independent of the sram paging bits in the cpu_f register. for additional information, refer to the mvw_pp register on page 238 . 4.2.7 related registers cpu_f register on page 32 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,d5h mvw_pp page bits[2:0] rw : 0 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 45 5. interrupt controller this chapter presents the interrupt controller and its associated registers. the interrupt controller provides a mechanism for a hardware resource in psoc devices to change program executio n to a new address without regard to the current task being performed by the code being executed. for a quick referenc e of all psoc registers in address order, refer to the register reference chapter on page 187 . 5.1 architectural description a block diagram of the interrupt controller is shown in figure 5-1 , illustrating the concepts of posted interrupts and pending interrupts . figure 5-1. interrupt controller block diagram this is the sequence of even ts that occur during interrupt processing. 1. an interrupt becomes active, either because (a) the interrupt condition occurs (for example, a timer expires), (b) a previously posted interrupt is enabled through an update of an interrupt mask register, or (c) an interrupt is pending and gie is set from ?0? to ?1? in the cpu flag register. 2. the current executing instruction finishes. 3. the internal interrupt service routine (isr) executes, tak- ing 13 cycles. during this time, the following actions occur: the pch, pcl, and flag register (cpu_f) are pushed onto the stack (in that order). the cpu_f register clears. since this clears the gie bit to ?0?, additional interrupts are temporarily disabled. the pch (pc[15:8]) is cleared to zero. the interrupt vector is read from the interrupt controller and its value is placed into pcl (pc[7:0]). this sets the program counter to point to the appropriate address in the interrupt table (for example, 0014h for the gpio interrupt). m8c core interrupt source (timer, gpio, etc.) interrupt taken or posted interrupt pending interrupt gie interrupt vector mask bit setting d r q 1 priority encoder interrupt request ... int_mskx int_clrx:n write cpu_f[0] ... [+] feedback
46 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c interrupt controller 4. program execution vectors to the interrupt table. typi- cally an ljmp instruction in the interrupt table sends exe- cution to the user's interrupt service routine for this interrupt. (see instruction set summary on page 28 .) 5. the isr executes. interrupts are disabled since gie = 0. in the isr, interrupts can be re-enabled if necessaty by setting gie = 1 (take care to avoid stack overflow in this case). 6. the isr ends with an reti instruction. this pops the flag register, pcl, and pch from the stack, restoring those registers. the restored flag register re-enables interrupts since gie = 1 again. 7. execution resumes at the next instruction, after the instruction that occurred before the interrupt. however, if there are more pending interrupts, the subsequent inter- rupts are processed before the next normal program instruction. interrupt latency. the time between the assertion of an enabled interrupt and the start of its isr is calculated using this equation: latency = time for current instruction to finish + time for m8c to change program counter to interrupt address + time for ljmp instruction in interrupt table to execute. equation 1 for example, if the 5-cycle jmp instruction is executing when an interrupt becomes active, the total number of cpu clock cycles before the isr begins is: equation 2 in this example, at 24 mhz, 25 clock cycles take 1.042 s. interrupt priority. interrupt priorities come into consider- ation when more than one interrupt is pending during the same instruction cycle. in th is case, the priority encoder (see figure 5-1 ) generates an interrupt vector for the highest priority pending interrupt. 5.1.1 posted versus pending interrupts an interrupt is posted when its interrupt conditions occur. this results in the flip-flop in figure 5-1 clocking in a 1. the interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate int_clrx register. a posted interrupt is not pending unless it is enabled by set- ting its interrupt mask bit (in the appropriate int_mskx reg- ister). all pending interrupts are processed by the priority encoder to determine the highest priority interrupt taken by the m8c if the global interrupt enable bit is set in the cpu_f register. disabling an interrupt by clearing its interrupt mask bit (in the int_mskx register) does not clear a posted interrupt, nor does it prevent an interrupt from posting. it simply prevents a posted interrupt from becoming pending. it is especially important to understand the functionality of clearing posted interrupts, if the configuration of the psoc device is changed by the application. for example, if a block has a posted interrupt when it is enabled and then disabled, the posted interrupt remains. therefore, it is good practice to use the int_clr register to clear posted interrupts before enabling or re-enabling a block. 5.2 application overview the interrupt controller and its associated registers allow the user?s code to respond to an interrupt from almost every functional block in psoc devices. interrupts for all the digital blocks and each of the analog co lumns are available, as well as interrupts for supply voltage, sleep, variable clocks, and a general gpio (pin) interrupt. the registers associated with the interrupt controller allow for the disabling of interrupts either globally or individually. the registers also provide a mechanism by which a user can clear all pending and posted interrupts or clear individual posted or pending interrupts. a software mechanism is pro- vided to set individual interrupts. setting an interrupt by way of software is very useful during code development, when one may not have the comple te hardware system necessary to generate a real interrupt. latency = time for current instruction to finish + time for m8c to change program counter to interrupt address + time for ljmp instruction in interrupt table to execute. (1 to 5 cycles for jmp to finish) + (13 cycles for interrupt routine) + (7 cycles for ljmp) = 21 to 25 cycles. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 47 interrupt controller the following table lists the interrupts and priorities that are available in the psoc devices. table 5-1. device interrupts interrupt priority interrupt address interrupt name 0 (highest) 0000h reset 1 0004h supply voltage monitor 2 0008h analog 3 000ch truetouch 4 0010h timer0 5 0014h gpio 6 0018h spi 7 001ch i2c 8 0020h sleep timer 9 0024h timer1 10 0028h timer2 23 (lowest) 005ch adc [+] feedback
48 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c interrupt controller 5.3 register definitions the following registers are associated with the interrupt controller and are listed in address order. the register descriptions have an associated register table showing the bit structure for that register. the bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions th at follow. always write reserved bits with a value of ?0?. fo r a complete table of interrupt cont roller registers, refer to the summary table of the core registers on page 24 . 5.3.1 int_clr0 register the interrupt clear register 0 (int_clr0) enables the indi- vidual interrupt sources? ability to clear posted interrupts. the int_clr0 register is similar to the int_msk0 register in that it holds a bit for ea ch interrupt source. functionally the int_clr0 register is similar to the int_vc register, although its operation is completely independent. when the int_clr0 register is read, any bits that are set indicate an interrupt was posted for that hardware resource. reading this register gives the user t he ability to determine all posted interrupts. the enable software interrupt (enswint) bit in the int_sw_en register determines how an individual bit value, written to an int_clr0 register, is interpreted. when enswint is cleared (the defaul t state), writing 1's to the int_clr0 register has no effect. however, writing 0's to the int_clr0 register, when enswint is cleared, causes the corresponding interrupt to clear . if the enswint bit is set, any 0's written to the int_clr0 register are ignored. how- ever, 1's written to the int_clr0 register, while enswint is set, cause an interrupt to post for the corresponding inter- rupt. software interrupts aid in debugging interrupt service rou- tines by eliminating the need to create system level interac- tions that are sometimes necessary to create a hardware- only interrupt. bit 7: i2c. this bit allows posted i2c interrupts to be read, cleared, or set. bit 6: sleep. this bit allows posted sleep interrupts to be read, cleared, or set. bit 5: spi. this bit allows posted spi interrupts to be read, cleared, or set. bit 4: gpio. this bit allows posted gpio interrupts to be read, cleared, or set. bit 3: timer0. this bit allows posted timer interrupts to be read, cleared, or set. bit 2: truetouch. this bit allows posted truetouch inter- rupts to be read, cleared, or set. bit 1: analog. this bit allows posted analog interrupts to be read, cleared, or set. bit 0: v monitor. this bit allows posted voltage monitor interrupts to be read, cleared, or set. for additional information, refer to the int_clr0 register on page 242 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,dah int_clr0 i2c sleep spi gpio timer0 truetouch analog v monitor rw : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 49 interrupt controller 5.3.2 int_clr1 register this register enables the indivi dual interrupt sources' ability to clear posted interrupts. when bits in this register are read, a '1' is returned for every bit position that has a corresponding posted interrupt. when bits in this register are written with a '0' and enswint is not set, posted interrupts are cleared at the corresponding bit positions. if there is no posted interrupt, there is no effect. when bits in this register are written with a '1' and enswint is set, an interrupt is posted in the interrupt controller. bit 7: endpoint3. read '0', no posted interrupt for usb endpoint3. read '1', posted interrupt present for usb endpoint3. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswin t = 1. post an interrupt for usb endpoint3. bit 6: endpoint2. read '0', no posted interrupt for usb endpoint2. read '1', posted interrupt present for usb endpoint2. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswin t = 1. post an interrupt for usb endpoint2. bit 5: endpoint1. read '0', no posted interrupt for usb endpoint1. read '1', posted interrupt present for usb endpoint1. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswin t = 1. post an interrupt for usb endpoint1. bit 4: endpoint0. read '0', no posted interrupt for usb endpoint0. read '1', posted interrupt present for usb endpoint0. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. post an interrupt for usb endpoint0. bit 3: usb sof. read '0', no posted interrupt for usb start of frame (sof). read '1', po sted interrupt present for usb start of frame (sof). write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. post an interrupt for usb start of frame (sof). bit 2: usb bus rst. read '0', no posted interrupt for usb bus reset. read '1', posted interrupt present for usb bus reset. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. po st an interrupt for usb bus reset. bit 1: timer2. read '0', no posted interrupt for timer2. read '1', posted interrupt present for timer2. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. po st an interrupt for timer2. bit 0: timer1. read '0', no posted interrupt for timer1. read '1', posted interrupt present for timer1. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. po st an interrupt for timer1. for additional information, refer to the int_clr1 register on page 244 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,dbh int_clr1 endpoint3 endpoint2 endpoint1 endpoint0 usb sof usb bus rst timer2 timer1 rw : 00 [+] feedback
50 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c interrupt controller 5.3.3 int_clr2 register this register enables the individual interrupt sources' ability to clear posted interrupts. when bits in this register are read, a '1' is returned for every bit position that has a corresponding posted interrupt. when bits in this register are written with a '0' and enswint is not set, posted interrupts are cleared at the corresponding bit positions. if there was not a posted interrupt, there is no effect. when bits in this regi ster are written with a '1' and enswint is set, an interrupt is posted in the interrupt con- troller. bit 5: usb_wake. read ?0?, no posted interrupt for usb wakeup. read ?1?, posted interrupt present for usb wakeup. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. post an interrupt for usb wakeup. bit 4: endpoint8. read ?0?, no posted interrupt for usb endpoint8. read ?1?, posted interrupt present for usb endpoint8. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. post an interrupt for usb endpoint8. bit 3: endpoint7. read ?0?, no posted interrupt for usb endpoint7. read ?1?, posted interrupt present for usb endpoint7. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. post an interrupt for usb endpoint7. bit 2: endpoint6. read ?0?, no posted interrupt for usb endpoint6. read ?1?, posted interrupt present for usb endpoint6. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. post an interrupt for usb endpoint6. bit 1: endpoint5. read ?0?, no posted interrupt for usb endpoint5. read ?1?, posted interrupt present for usb endpoint5. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. post an interrupt for usb endpoint5. bit 0: endpoint4. read ?0?, no posted interrupt for usb endpoint4. read ?1?, posted interrupt present for usb endpoint4. write 0 and enswint = 0. clear posted interrupt if it exists. write 1 and enswint = 0. no effect. write 0 and enswint = 1. no effect. write 1 and enswint = 1. post an interrupt for usb endpoint4. for additional information, refer to the int_clr2 register on page 246 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,dch int_clr2 usb_wake endpoint8 endpoint7 endpoint6 endpoint5 endpoint4 rw : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 51 interrupt controller 5.3.4 int_msk0 register the interrupt mask register (int_msk0) enables the indi- vidual interrupt sources? ability to create pending interrupts. if cleared, each bit in an int_msk0 register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). however, an interrupt can still post even if its mask bit is zero. all int_msk0 bits are indepen- dent of all other int_msk0 bits. if an int_msk0 bit is set, the interrupt source associated with that mask bit may generate an interrupt that becomes a pending interrupt. for example, if int_msk0[4] is set and at least one gpio pin is configured to generate an interrupt, the interrupt controller allows a gpio interrupt request to post and become a pending interrupt to which the m8c responds. if a higher priority interrupt is generated before the m8c responds to the gpio interrupt, the higher priority interrupt is responded to before the gpio interrupt. each interrupt source may require configuration at a block level. refer to the corresponding chapter for each interrupt for any additional configuration information. bit 7: i2c. this bit allows i2c interrupts to be enabled or masked. bit 6: sleep. this bit allows sleep interrupts to be enabled or masked. bit 5: spi. this bit allows spi interrupts to be enabled or masked. bit 4: gpio. this bit allows gpio interrupts to be enabled or masked. bit 3: timer0. this bit allows timer0 interrupts to be enabled or masked. bit 2: truetouch. this bit allows truetouch interrupts to be enabled or masked. bit 1: analog. this bit allows analog interrupts to be enabled or masked. bit 0: v monitor. this bit allows voltage monitor interrupts to be enabled or masked. for additional information, refer to the int_msk0 register on page 250 . 5.3.5 int_msk1 register this register enables the individual sources' ability to create pending interrupts. when an interrupt is masked off, the mask bit is '0'. the interrupt continues to post in the interrupt controller. clear- ing the mask bit only prevents a posted interrupt from becoming a pending interrupt. bit 7: endpoint3. ?0? is mask usb endpoint3 interrupt. ?1? is unmask usb endpoint3 interrupt. bit 6: endpoint2. ?0? is mask usb endpoint2 interrupt. ?1? is unmask usb endpoint2 interrupt. bit 5: endpoint1. ?0? is mask usb endpoint1 interrupt. ?1? is unmask usb endpoint1 interrupt. bit 4: endpoint0. ?0? is mask usb endpoint0 interrupt. ?1? is unmask usb endpoint0 interrupt. bit 3: usb sof. ?0? is mask usb sof interrupt. ?1? is unmask usb sof interrupt. bit 2: usb bus reset(k). ?0? is mask usb bus reset interrupt. ?1? is unmask usb bus reset interrupt. bit 1: timer2. ?0? is mask timer2 interrupt. ?1? is unmask timer2 interrupt. bit 0: timer1. ?0? is mask timer1 interrupt. ?1? is unmask timer1 interrupt. for additional information, refer to the int_msk1 register on page 249 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,e0h int_msk0 i2c sleep spi gpio timer0 truetouch analog v monitor rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,dfh int_msk1 endpoint3 endpoint2 endpoint1 endpoint0 usb sof usb bus reset timer2 timer1 rw : 00 [+] feedback
52 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c interrupt controller 5.3.6 int_msk2 register this register is used to enable the individual sources' ability to create pending interrupts. when an interrupt is masked off, the mask bit is '0'. the interrupt still posts in the in terrupt controller. therefore, clearing the mask bit only prevents a posted interrupt from becoming a pending interrupt. bit 5: usb wakeup. ?0? is mask usb wakeup interrupt. ?1? is unmask usb wakeup interrupt. bit 4: endpoint8. ?0? is mask usb endpoint8 interrupt. ?1? is unmask usb endpoint8 interrupt. bit 3: endpoint7. ?0? is mask usb endpoint7 interrupt. ?1? is unmask usb endpoint7 interrupt. bit 2: endpoint6. ?0? is mask usb endpoint6 interrupt. ?1? is unmask usb endpoint6 interrupt. bit 1: endpoint5. ?0? is mask usb endpoint5 interrupt. ?1? is unmask usb endpoint5 interrupt. bit 0: endpoint4. ?0? is mask usb endpoint4 interrupt. ?1? is unmask usb endpoint4 interrupt. for additional information, refer to the int_msk2 register on page 248 . 5.3.7 int_sw_en register the interrupt software enable register (int_sw_en) is used to enable software interrupts. bit 0: enswint. this bit is a special non-mask bit that controls the behavior of t he int_clr0 register. see the int_clr0 register in this section for more information. for additional information, refer to the int_sw_en register on page 251 . 5.3.8 int_vc register the interrupt vector clear re gister (int_vc) returns the next pending interrupt and clears all pending interrupts when written. bits 7 to 0: pendin g interrupt[7:0]. when the register is read, the least significant byte (lsb) of the highest priority pending interrupt is returned. for example, if the gpio and i2c interrupts were pending and the int_vc register was read, the value 14h is read. however, if no interrupts were pending, the value 00h is returned. this is the reset vector in the interrupt table; however, reading 00h from the int_vc register is not considered an indication that a system reset is pending. rather, reading 00h from the int_vc register sim- ply indicates that there are no pending interrupts. the high- est priority interrupt, indicated by the value returned by a read of the int_vc register, is removed from the list of pending interrupts when the m8c services an interrupt. reading the int_vc register has limited usefulness. if inter- rupts are enabled, a read to the int_vc register is not able to determine that an interrupt was pending before the inter- rupt was actually taken. however, while in an interrupt ser- vice routine, a user may wish to read the int_vc register to see the next interrupt. when the int_vc register is written address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,deh int_msk2 usb wakeup endpoint8 endpoint7 endpoint6 endpoint5 endpoint4 rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,e1h int_sw_en enswint rw : 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,e2h int_vc pending interrupt[7:0] rc : 00 legend clearable register or bits. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 53 interrupt controller with any value, all pending and posted interrupts are cleared by asserting the clear line for each interrupt. for additional information, refer to the int_vc register on page 252 . 5.3.9 related registers cpu_f on page 254 . [+] feedback
54 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c interrupt controller [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 55 6. general purpose i/o (gpio) this chapter discusses the general purpose i/o (gpio) and its associated registers, which is the circuit responsible for inter- facing to the i/o pins of a psoc device. the gpio blocks prov ide the interface between the m8c core and the outside world. they offer a large number of conf igurations to support several types of input/out put (io) operations for both digital and analo g systems. for a complete table of the gpio registers, refer to the psoc core on page 23 . for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 6.1 architectural description the gpio in the cy8ctmg20x, cy8ctst200 devices are all unif orm, except that port 0 and port 1 gpio have stronger high drive. in addition to higher drive st rength, port 1 gpio have an option for regulat ed output level. thes e distinctions are discussed in more detail in the section port 1 distinctions on page 56 and port 0 distinctions on page 57 . figure 6-1. gpio block diagram drive logic dm1 dm0 alt. select write prtxdr alt. data 2:1 vdd note alt. select/ data is not available on all pins. vdd 5.6k ldo reg_en port 1 only vdd pin drive modes dm1 drive mode dm0 diagram number data = 0 data = 1 alt. input (e.g., i2c) data bus read prtxdr dm(1:0) = 10b inbuf (to gpio interrupt logic) note no diode to vdd for port 1 0 0 1 1 0 1 0 1 resistive pull up strong drive high impedance open drain 0 1 2 3 strong strong an. high z strong resistive strong high z high z 0. 1. 2. 3. [+] feedback
56 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c general purpose i/o (gpio) 6.1.1 general description the gpio contains input buffers , output drivers, and config- uration logic for connecting the psoc device to the outside world. io ports are arranged with (up to) 8 bits per port. each full port contains eight identical gpio blocks. each gpio block is used for the following types of i/o: digital i/o (digital input and output controlled by soft- ware) analog i/o each i/o pin also has several drive modes, and interrupt capabilities. all gpio pins provide both digital i/o and ana- log input capability. all i/o contain the capability to connect to an internal analog bus. this is described in detail in the i/o analog multiplexer chapter on page 99 . certain pins contain an option to bypass the normal data path and output from an internal source. an example is i2c outputs. these are described in data bypass on page 58 . 6.1.2 digital i/o one of the basic operations of the gpio ports is to allow the m8c to send information out of the psoc device and get information into the m8c from outside the device. this is accomplished by way of the por t data register (prtxdr). writes from the m8c to the pr txdr register store the data state, one bit per gpio. in the standard non-bypass mode, the pin drivers drive the pin in response to this data bit, with a drive strength determined by the drive mode setting (see figure 6-1 ). the actual voltage on the pin depends upon the drive mode and the external load. the m8c reads the value of a port by reading the prtxdr register address. when the m8c reads the prtxdr register address, the current value of the pin voltage is translated into a logic value and returned to the m8c. note that the pin voltage can represent a different logic value than the last value written to the prtxdr register. this is an important distinction to remember in situ ations such as the use of a read modify write to a prtxdr register. examples of read modify write instructions include and, or, and xor. the following is an example of how a read modify write, to a prtxdr register, could have an unexpected and even inde- terminate result in certain systems. consider a scenario where all bits of port 1 on the psoc device are in the strong 0 resistive 1 drive mode; so t hat in some cases, the system the psoc is in may pull down one of the bits by an external driver. mov reg[prt1dr], 0xff and reg[prt1dr], 0x7f in the first line of this code, writing a 0xff to the port causes the psoc to drive all pins high through a resistor. this does not affect any bits that are st rongly driven low by the system the psoc is in. however, in the second line of code, it can- not guarantee that only bit 7 is the one set to a strong 0 (zero). because the and instruct ion first reads the port, any bits that are currently driven low externally are read as a 0. these zeros are then written back to the port. when this happens, the pin goes into a strong 0 state; therefore, if the external low drive condition ends in the system, the psoc keeps the pin value at a logic 0. 6.1.3 analog and digital inputs analog signals pass into the psoc device core from device pins through a resistive path. for analog signals, the gpio block is typically configured into a high impedance analog drive mode (high z). the mode turns off the schmitt trigger on the input path, which ma y reduce power consumption and decrease internal switching noise when using a particu- lar i/o as an analog input. all modes, except high impedance analog, allow digital inputs. the most useful digital input modes are resistive pull up (dm1, dm0 = 00b with data = 1) or a fully high impedance input using open drain (dm1, dm0 = 11b with data = 1). 6.1.4 port 1 distinctions port 1 has two differences from the other gpio ports. it has stronger high drive (as does port 0) and it has an option for regulating all outputs to a 3v/2.5v/1.8v level when in strong drive mode. refer to the device data sheet for the different current sourcing specifications of port 1. by setting the reg_en bit in the io_cfg1 register, port 1 can be configured to drive strong high to a regulated 3v/ 2.5v/1.8v level. if reg_en is set low, port 1 pins drive to vdd in strong drive mode. in resistive high drive mode ([dm1, dm0] = 00), the pins pull up to the chip vdd level regardless of the regulator set- ting for this port. only strong drive mode allows for the out- puts to be driven to the regulated level. when the reg_en bit is set high, pins configured for strong drive to regulated level, while those in resistive pull up mode drive to vdd. in their default state, all port 1 i/o prevent dc current from flowing into the pin when the pin voltage is above the chip vdd. this feature resolves the problem where the psoc holds down the system i2c bus or provides a current leak- age path from a powered peripheral during psoc power down or reset. the open drain driver is capable of sinking 24 ma current (required for sinking leds used for backlighting) and main- taining a logic low state. regulated output level can be selected by bits 4 and 5 in the io_cfg1 register. for 3v output level, the chip vdd should be greater than 3.1v. for 2.5v output, the chip vdd should [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 57 general purpose i/o (gpio) be greater than 2.7v, and for 1.8v output level, chip vdd should be greater than 2.5v. 6.1.5 port 0 distinctions port 0 has a stronger high drive. however, unlike port 1, it does not have an option for regulating the outputs when in strong drive mode. refer to the device data sheet for the dif- ferent current sourcing specifications of port 0. 6.1.6 gpio block interrupts you have the ability to individual ly configure each gpio pin for interrupt capability. pins are configured by pin interrupt enables and also by a chip wide selection for interrupt state with this global selection. pins can be set to interrupt when the pin is low or when it changes from the last time it was read. the block provides an open drain interrupt output (into) that is connected to other gpio blocks in a wire-or fashion. all pin interrupts that are wire-or?ed together are tied to the same system gpio interrupt. therefore, if interrupts are enabled on multiple pins, the us er?s interrupt service routine must provide a mechanism to determine which pin was the source of the interrupt. using a gpio interrupt requires these steps: 1. set the interrupt mode (ioint bit in the io_cfg1 regis- ter). 2. enable the bit interrupt in the gpio block. 3. set the mask bit for t he (global) gpio interrupt. 4. assert the overall global interrupt enable. the first step sets a common interrupt mode for all pins. the second step, bit interrupt enable, is set at the gpio pin level (that is, at each port pin), by way of the prtxie regis- ters. the last two steps are common to all interrupts and described in the interrupt controller chapter on page 45 . at the gpio block level, asserting the into line depends only on the bit interrupt enable and the state of the pin rela- tive to the chosen interrupt mode. at the psoc device level, due to their wire-or nature, the gpio interrupts are neither true edge sensitive interrupts nor true level sensitive inter- rupts. they are considered edge sensitive for asserting, but level sensitive for release of the wire-or interrupt line. if no gpio interrupts are asserting, a gpio interrupt occurs whenever a gpio pin interrupt enable is set and the gpio pin transitions (if not already transitioned) appropriately high or low to match the interrupt mode configuration. after this happens, the into line pulls low to assert the gpio inter- rupt. this assumes the othe r system level enables are on, such as setting the global gpio interrupt enable and the global interrupt enable. setting the pin interrupt enable may immediately assert into, if the interrupt mode conditions are already being met at the pin. after into pulls low, it continues to hold into low until one of these conditions change: the pin interrupt enable is cleared. the voltage at pin transitions to the opposite state. in interrupt-on-change mode, the gpio data register is read thus setting the local interrupt level to the opposite state. the interrupt mode is changed so that the current pin state does not create an interrupt. after one of these conditions is met, the into releases. at this point, another gpio pin (or this pin again) could assert its into pin, pulling the common line low to assert a new interrupt. note the following behavior from this level release feature. if one pin is asserting into and then a second pin asserts its into, when the first pin releases its into, the second pin is already driving into and thus no change is seen (that is, no new interrupt is asserted on the gpio interrupt). take care, using polling or the states of the gpio pin and global inter- rupt enables, to catch all interrupts among a set of wire-or gpio blocks. figure 6-2. gpio interrupt logic diagram 6.1.6.1 interrupt modes gpio interrupts use the ioint bit from the io_cfg1 regis- ter. the setting of ioint determines the interrupt mode for all gpio. interrupt mode ioint=0 means that the block asserts the gpio interrupt line (into) when the pin voltage is low, if the block?s bit interrupt enable line is set (high). interrupt mode ioint=1 means that the block asserts the interrupt line (into) when the pin voltage is the opposite of the last state read from the pi n, if the block?s bit interrupt enable line is set high. this mode switches between low mode and high mode, depending upon the last value read from the port during reads of the data register (prtxdr). if the last value read from the gp io was 0, the gpio pin is in ie (prtxie.n) ioint port read dq into inbuf (from gpio block diagram) interrupt mode ioint ie interrupt 00 disabled 01 disabled 10 low 1 1 change from last read [+] feedback
58 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c general purpose i/o (gpio) interrupt high mode. if the last value read from the gpio was ?1?, the gpio is in interrupt low mode. figure 6-3 assumes that the gie is set, gpio interrupt mask is set, and that the ioint bit was set to high. the change interrupt mode relies on the value of an internal read register to determine if the pin stat e changed. therefore, the port that contains the gpio in question must be read during every interrupt service routine. if the port is not read, the interrupt mode acts as if it is in high mode when the latch value is ?0? and low mode when the latch value is ?1?. figure 6-3. gpio interrupt mode ioint = 1 6.1.7 data bypass gpio pins are configured to either output data through cpu writes to the prtxdr registers or to bypass the port's data register and output data from in ternal functions instead. the bypass path is shown in figure 6-1 by the alt data input, which is selected by the alt select input. these data bypass options are selected in one of two ways. for internal functions such as i2c and spi, the hardwire automatically sele cts the bypass mode for the required pins when the function is enabled. in addition, some bypass outputs are selected by the user through the out_p1 register. for these, the pin is configured for data bypass when the register bit is set high, which allows an internal signal to be driven to the pin. for all bypass modes, the wanted drive mode of the pin must be configured separately for each pin, with the prtxdm1 and prtxdm0 registers. table 6-1. gpio interrupt modes ie ioint description 0 0 bit interrupt disabled, into deasserted 0 1 bit interrupt disabled, into d-asserted 1 0 assert into when pin = low 1 1 assert into when pin = change from last read last value read from pin was ?0? pin state waveform interrupt occurs (a) pin state waveform gpio pin interrupt enable set interrupt occurs (b) gpio pin interrupt enable set last value read from pin was ?1? pin state waveform gpio pin interrupt enable set interrupt occurs (c) pin state waveform gpio pin interrupt enable set interrupt occurs (d) [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 59 general purpose i/o (gpio) 6.2 register definitions the following registers are associated with the general purpose i/o (gpio) and ar e listed in address order. the register descriptions have an associated register table showing the bit stru cture for that register. the bits in the tables that are gra yed out are reserved bits and are not detailed in the register descrip tions that follow. always write reserved bits with a value of 0. for a complete table of general pu rpose i/o registers, refer to the core register summary on page 24 . for a selected gpio blo ck, the individual registers are addressed in the core register summary on page 24 . in the register names, the ?x? is the port number, configur ed at the psoc device level (x = 0 to 4 typically). all register values are readabl e, except for the prtxdr register; reads of this register return the pin state instead of the register bit state. 6.2.1 prtxdr registers the port data register (prtxdr) allows for write or read access of the current logical equivalent of the voltage on the pin. bits 7 to 0: data[7:0]. writing the prtxdr register bits set the output drive state fo r the pin to high (for data = 1) or low (data = 0), unless a bypass mode is selected (see data bypass on page 58 ). reading the prtxdr register returns the actual pin state, as seen by the input buffer. this may not be the same as the expected output state, if the load pulls the pin more strongly than the pin?s configur ed output drive. see digital i/o on page 56 for a detailed discussion of digital i/o. for additional information, refer to the prtxdr register on page 188 . 6.2.2 prtxie registers the port interrupt enables (prtxie) registers enable or dis- able interrupts from individual gipio pins. bits 7 to 0: interruptenables[7:0]. these bits enable the corresponding port pin interrupt. only four lsb pins are used since this port has four pins. ?0? is port pin interrupt disabled for the corresponding pin. ?1? is port pin interrupt enabled for the corresponding pin. interrupt mode is determined by the ioint bit in the io_cfg1 register. for additional information, refer to the prtxdr register on page 188 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,xxh prtxdr data[7:0] rw : 00 legend xx an ?x? after the comma in the address field indicates that there are multiple instances of the register. for an expanded addr ess listing of these registers, refer to the core register summary on page 24 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,xxh prtxie interruptenables[7:0] rw : 00 legend xx an ?x? after the comma in the address field indicates that there are multiple instances of the register. for an expanded addr ess listing of these registers, refer to the core register summary on page 24 . [+] feedback
60 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c general purpose i/o (gpio) 6.2.3 prtxdmx registers the port drive mode bit registers (prtxdm0 and prtxdm1) specify the drive mode for gpio pins. bits 7 to 0: drive mode x[7:0]. in the prtxdmx registers there are four possible drive modes for each port pin. two mode bits are required to select one of these modes, and these two bits are spread into two different registers (prtxdm0 and prtxdm1). the bit position of the affected port pin (for example, pin[2] in port 0) is the same as the bit position of each of the two drive mode register bits that con- trol the drive mode for that pin (for example, bit[2] in prt0dm0 and bit[2] in prt0dm1). the two bits from the two registers are treated as a group. these are referred to as dm1 and dm0, or together as dm[1:0]. drive modes are shown in ta b l e 6 - 3 . for analog i/o, set the drive mode to the high z analog mode, 10b. the 10b mode disables the block?s digital input buffer so no crowbar current flows, even when the analog input is not close to either power rail. if the 10b drive mode is used, the pin is always read as a zero by the cpu and the pin cannot generate a useful in terrupt. (it is not strictly required that you select high z mode for analog operation.) when digital inputs are needed on the same pin as analog inputs, use the 11b drive mode with the corresponding data bit (in the prtxdr register) set high. the gpio provides a default drive mode of high impedance, analog (high z). this is achieved by forcing the reset state of all prtxdm1 registers to ffh. for additional information, refer to the prtxdm0 register on page 259 , and the prtxdm1 register on page 260 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,xxh prtxdm0 drive mode 0[7:0] rw : 00 1,xxh prtxdm1 drive mode 1[7:0] rw : ff legend xx an ?x? after the comma in the address field indicates that there are multiple instances of the register. for an expanded addr ess listing of these registers, refer to the core register summary on page 24 . drive modes pin state description dm1 dm0 0 0 resistive pull up resistive high, strong low 0 1 strong drive strong high, strong low 10 high impedance, analog ( reset state ) high z high and low, digital input dis- abled (for zero power) ( reset state ) 1 1 open drain low high z high (digital input enabled), strong low. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 61 general purpose i/o (gpio) 6.2.4 io_cfg1 register the input/output conf iguration register 1 (io_cfg1) con- figures the port 1 output r egulator and set the interrupt mode for all gpio. bit 7: strongp. setting this bit increases the drive strength and edge ratio for high outputs. bit 5 and 4: range[1:0]. these bits select the regulator output level for port 1. available levels are 3.0v, 1.8v, and 2.5v. selects the high output level for port 1 outputs. bit 3 p1_low_thrs. this bit reduces the threshold volt- age of the p1 port input buffers so that there are no compat- ibility issues when port 1 is communicating at regulated voltage levels. ?0? is standard threshold of vi h, vil. ?1? is reduce threshold of vih, vil. bit 2: spiclk_on_p10. when this bit is set to ?1?, the spi clock is mapped to port 1 pin 0. otherwise, it is mapped to port 1 pin 3. bit 1: reg_en. the register enable bit (reg_en) con- trols the regulator on port 1 outputs. bit 0: io int. this bit sets the gpio interrupt mode for all pins in the cy8ctmg20x, cy8ctst200 psoc devices. gpio interrupts are controlled at each pin by the prtxie registers, and also by the global gpio bit in the int_msk0 register. for additional information, refer to the io_cfg1 register on page 272 . 6.2.5 io_cfg2 register the input/output configuration register 2 (io_cfg2) selects output regulated supply and clock rates. bits 5 to 3: reg_level[2:0]. these bits select output regulated supply. bits 1 to 0: reg_clock[1:0]. the regulated i/o charge pump can operate with a maximum clock speed of 12 mhz. the reg_clock[1:0] bits select clocking options for the regulator. setting reg_clock[1:0] to ?10? should be used with 24 mhz sysclk and ?01? should be used with 6/12 mhz sysclk. for additional information, refer to the io_cfg2 register on page 275 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,dch io_cfg1 strongp range[1:0] p1_low_ thrs spiclk_ on_p10 reg_en ioint rw : 00 range[1:0] output level 00 3.0 volts 01 3.0 volts 10 1.8 volts 11 2.5 volts address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,deh io_cfg2 reg_level[2:0] reg_clock[1:0] rw : 00 reg_level[2:0] approx. regulated supply (v) 000 3 2.5 1.8 001 3.1 2.6 1.9 010 3.2 2.7 2.0 011 3.3 2.8 2.1 100 3.4 2.9 2.2 101 3.5 3.0 2.3 110 3.6 3.1 2.4 111 3.7 3.2 2.5 reg_clock[1:0] sysclk clock rate 10 24 mhz 01 6/12 mhz [+] feedback
62 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c general purpose i/o (gpio) [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 63 7. internal main oscillator (imo) this chapter presents the internal main oscillator (imo) and its associated register s. the imo produces clock signals of 6, 12, and 24 mhz. for a complete table of the imo registers, refer to the summary table of the core registers on page 24 . for a quick reference of allpsoc registers in address order, refer to the register reference chapter on page 187 . 7.1 architectural description the internal main oscillator (imo) outputs a clock that is normally driven to the main system clock, sysclk. the imo clock frequency can be configured as 6, 12, or 24 mhz. the accuracy of the internal imo clock is approximately 5% over temperature and voltage variation. no external components are required to achieve this level of accuracy. the imo provides higher accuracies when enabled for lock- ing to usb traffic during usb operation. see full-speed usb chapter on page 165 for more information. the imo can be disabled when using an external clocking source. also, the frequency doubler circuit, which produces sysclkx2, can be disabled to save power. when using an external clock, and sysclkx2 is needed, you cannot dis- able the imo. registers for controlling these operations are found in the digital clocks chapter on page 109 . 7.2 application overview device power may be optimized by selecting among the 24, 12, or 6 mhz settings using the slimo bits in the cpu_scr1 register in conjunction with associated trim val- ues in the imo_tr register . both methods are described ahead. 7.2.1 trimming the imo an 8-bit register (imo_tr) is used to trim the imo. bit 0 is the lsb and bit 7 is the msb. the trim step size is approxi- mately 60 khz at the 24 mhz clock setting. a factory trim setting is loaded into the imo_tr register at boot time. 7.2.2 engaging slow imo writing to the slimo bits of the cpu_scr1 register enables the slow imo feature. slimo settings for 6 and 12 mhz are listed in ta b l e 7 - 1 . when changing frequency ranges, the associated factory trim value must be loaded into the imo_tr register. the imo immediately changes to the new frequency. factory trim settings are stored in flash for the frequencies listed in table 7-1 . table 7-1. imo frequencies slimo cy8ctmg20x, cy8ctst200 00 12 01 6 10 24 11 reserved [+] feedback
64 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c internal main oscillator (imo) 7.3 register definitions the following registers are associated with the internal main os cillator (imo). the register de scriptions have associated reg- ister tables showing the bit structure for that register. the bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow. always write reserved bits with a value of ?0?. for a complete table showing all oscillator registers, refer to the summary table of the core registers on page 24 . 7.3.1 imo_tr register the internal main oscillator trim register (imo_tr) manu- ally centers the oscillator's output to a target frequency. this register is loaded with a factory trim value at boot. when changing frequency ranges, the matching frequency trim value must be loaded into this register. a tableread command to the supervisory rom returns the trim values to the sram. eraseall parameters (05h), on page 36 has information on the location of various trim set- tings stored in flash tables. firmware needs to read the right trim value for desired frequency and update the imo_tr register. the imo_tr register must be changed at the lower frequency range setting. for additional informa tion, refer to the imo_tr register on page 281 7.3.2 imo_tr1 register the internal main oscillator trim register 1 (imo_tr1) adjusts the imo frequency . bits 2 to 0: fine trim[2:0]. these bits provide a fine tun- ing capability to the imo trim. these three bits are the 3 lsb of the imo trim with the imo_tr register supplying the 8 msb. a larger value in this register will increase the speed of the oscillator. the value in these bits varies the imo fre- quency: approximately 7.5 khz/step. when the enablelock bit is set in the usb_cr1 register, firmware writes to this register are disabled. for additional information, refer to the imo_tr1 register on page 286 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,e8h imo_tr trim[7:0] rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,fah imo_tr1 fine trim[2:0] rw : 0 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 65 internal main oscillator (imo) 7.3.3 cpu_scr1 register the system status and control register 1 (cpu_scr1) conveys the status and control of events related to internal resets and watchdog reset. bit 7: iress. the internal reset status bit is a read only bit that determines if the booting process occurred more than once. when this bit is set, it indi cates that the srom swbootre- set code ran more than once. if this bit is not set, the swbootreset ran only once. in either case, the swbootre- set code does not allow executio n from code stored in flash until the m8c core is in a safe operating mode with respect to supply voltage and flash operation. there is no need for concern when this bit is set. it is provided for systems that may be sensitive to boot time, so that they can determine if the normal one pass boot time was exceeded. for more information on the swbootreest code, see the supervisory rom (srom) chapter on page 89 . bit 4 to 3: slimo[1:0]. these bits set the imo frequency range. see the table below for more information. these changes allow for optimization of speed and power. the imo trim value must also be changed when slimo is changed (see engaging slow imo on page 63 ). when not in external clocking m ode, the imo is the source for sysclk; therefore, when the speed of the imo changes so does sysclk. bit 0: iramdis. initialize ram disable. this bit is a control bit that is readable and writeable. the default value for this bit is ?0?, which indicates t hat the maximum amount of sram must be initialized upon watchdog reset to a value of 00h. when the bit is ?1?, the minimum amount of sram is initial- ized after a watchdog reset. for additional information, refer to the cpu_scr1 register on page 257 . 7.3.4 osc_cr2 register the oscillator control regist er 2 (osc_cr2) configures various features of internal clock sources and clock nets. bit 4: clk48men. this is the 48 mhz clock enable bit. ?0? disables the bit and ?1? enables the bit. this register setting applies only when the device is not in ocd mode. when in ocd mode, the 48 mhz clock is always active. bit 2: extclken. when the extclken bit is set, the external clock becomes the source for the internal clock tree, sysclk, which drives most device clocking functions. all external and internal signals, including the low speed oscillator, are synchronized to this clock source. the exter- nal clock input is located on p1[4]. when using this input, the pin drive mode must be set to high z (not high z ana- log), such as drive mode 11b with prt1dr bit 4 set high. bit 1: imodis. when set, the internal main oscillator (imo) is disabled. for additional information, refer to the osc_cr2 register on page 278 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access x,feh cpu_scr1 iress slimo[1:0] iramdis # : 0 legend x an ?x? before the comma in the address field indicates that this r egister can be read or written to no matter what bank is use d. # access is bit specific. refer to the register reference chapter on page 187 for additional information. slimo cy8ctmg20x, cy8ctst200 00 12 01 6 10 24 11 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,e2h osc_cr2 clk48men extclken imodis rw : 00 [+] feedback
66 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c internal main oscillator (imo) 7.3.5 related registers osc_cr2 register on page 115 . cpu_scr1 register on page 137 . . [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 67 8. internal low speed oscillator (ilo) this chapter briefly explains the internal low speed oscillato r (ilo) and its associated register. the internal low speed oscillator produces a 32 khz or 1 khz clock. for a quick refe rence of all psoc registers in address order, refer to the register reference chapter on page 187 . 8.1 architectural description the internal low speed oscillator (ilo) is an oscillator with a nominal frequency of 32 khz or 1 khz. it is used to generate sleep wakeup interrupts and watchdog resets. this oscillator is also used as a clocking source for the digital blocks. this block operates with a small internal bias current and produces an output clock of either 1 khz or 32 khz, configurable by the user. the ilo is trimmed for 32 khz in production devices. there is no trim for 1 khz, hence, high variation is expected from nominal value. the block operates by charging a capacitor with a current, to a reference level. once reached, the capacitor is discharged to ground. this process repeats to pr ovide the oscillator (half) period. [+] feedback
68 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c internal low speed oscillator (ilo) 8.2 register definitions the following register is associated with t he internal low speed oscillator (ilo). the register description has an associated register table showing the bit structure. the bits in the table that are grayed out are reserved bits and are not detailed in t he register description that follows. always write reserved bits with a value of ?0?. 8.2.1 ilo_tr register the internal low speed oscillator trim register (ilo_tr) sets the adjustment for the internal low speed oscillator. bit 6: pd_mode. this bit selects power down mode. set- ting this bit high disables the oscillator and current bias when the ilo is powered down, which results in slower star- tup time. setting this bit low keeps the small current bias running when the ilo is powered down, which results in faster startup time. bit 5: ilofreq. when this bit is set, the oscillator operates at a nominal frequency of 1 khz, otherwise, it runs at the default 32 khz. bits 3 to 0: freq_trim[3:0]. these bits trim the oscillator frequency. the device-specific va lue, placed in the trim bits of this register at boot time , is based on factory testing. do not alter the values in the register . for additional information, refer to the ilo_tr register on page 282 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,e9h ilo_tr pd_mode ilofreq freq trim[3:0] rw : 18 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 69 9. external crystal oscillator (eco) this chapter briefly explains the external crystal oscillator (e co) and its associated registers. the 32.768 khz external crys- tal oscillator circuit allows the user to replace the internal low speed oscillator with a more precise time source. for a quic k ref- erence of all psoc registers in address order, refer to the register reference chapter on page 187 . 9.1 architectural description the external crystal oscillator (eco) circuit requires only the following external components: an inexpensive watch crystal and two small value capacitors. the xtalin (p2[3]) and xtalout (p2[5]) pins connect to a 32.768 khz watch crystal and the two external capacitors bypass these pins to ground. figure 9-1 shows the external connections needed to implement the eco. see the application overview on page 70 for information on enabling the eco. transitions between the internal and external oscillator domains may produce glitches on the clock bus. during the process of activati ng the eco, there must be a hold-off period before using it as the 32.768 khz source. this hold-off period is partially implemented in hardware using the sleep timer. firmware must set up a sleep period of one second (maximum eco settling time), and then enable the eco in the osc_cr0 register. at the one sec- ond timeout (the sleep interrup t), the switch is made by hardware to the eco. if the eco is subsequently deacti- vated, the internal low spe ed oscillator (ilo) will again be activated and the switch is made back to the ilo immedi- ately. the eco exists bit (eco ex , bit 0 of eco_config) is used to control whether the switch-over is allowed or locked. this is a write once bit. it is written early in code execution after a power on reset (por ) or external reset (xres) event. a '1' in this bit indicates to the hardware that a crystal exists in the system, and firmware is allowed to switch back and forth between eco and ilo operation. if the bit is '0', switch-over to the eco is locked out. figure 9-1. external components for the eco the eco exists written bit (eco exw, bit 1 of eco_config) is read only and is set on the first write to this register. when this bit is '1 ', it indicates that the state of eco ex is locked. this is illustrated in figure 9-2 . p2[5] p2[3] vss vss vss x1 c1 c2 [+] feedback
70 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c external crystal oscillator (eco) figure 9-2. state transition between eco and ilo 9.2 application overview to use a 32.768 khz external crystal, the gpio pins that connect to the crystal must be set to the high impedance drive mode. see the general purpose i/o (gpio) chapter on page 55 for information on gpio s and their drive modes. the firmware steps involved in switching between the inter- nal low speed oscillator (ilo) to the 32.768 khz external crystal oscillator (eco) are as follows. at reset, the device begins operation using the ilo. 1. set the eco ex bit to allow crystal operation. 2. modify bits [2:0] in the external crystal oscillator enbus register to be 011b. 3. select a sleep interval of one second, using bits[4:3] in the oscillator control regist er 0 (osc_cr0), as the oscillator stabilization interval. 4. set bit [7] in the oscillator control register 0 (osc_cr0) to '1' to enable the external crystal oscilla- tor. 5. the eco becomes the selected source at the end of the one-second interval on the edge created by the sleep interrupt logic. the one-second interval gives the oscilla- tor time to stabilize before it becomes the active source. the sleep interrupt need not be enabled for the switch- over to occur. reset the sleep timer (if this does not interfere with any ongoing realtime clock operation), to guarantee the interval length. note that the ilo contin- ues to run until the oscillato r is automatic ally switched over by the sleep timer interrupt. note the ilo switches back instantaneously by writing the 32 khz select cont rol bit to '0'. note transitions between oscillator domains may produce glitches on the 32 khz clock bus. functions that require accuracy on the 32 khz clock should be enabled after the transition in oscillator domains. ilo inactive eco active ilo active eco inactive this transition is a llowed only if the write once "eco exists" register bit is set. default por state set osc_cr0[7] to activate the eco, then on the next sleep interrupt, eco becomes the 32.768 khz source. clear osc_cr0[7] to immediately revert back to ilo as 32 khz source. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 71 external crystal oscillator (eco) 9.3 register definitions these registers are associated with the external crystal oscillator. 9.3.1 eco_enbus register the eco_enbus register is used to disable and enable the external crystal oscillator (eco). bits 2 to 0 eco_enbus[2:0]. 111b ? default. disables the external crystal oscillator (eco). 011b ? allows the eco to be enabled by bits in the eco_cfg register. other values are reserved. see the application overview on page 70 for the proper sequence for enabling the eco. for additional information, refer to the eco_enbus regis- ter on page 269 . 9.3.2 eco_trim register the eco trim register (eco _trim) controls gain and power settings for the 32 khz crystal oscillator. these settings should not be changed from their default state. bits 4 to 2: eco_xgm[2:0]. these bits set the amplifier gain. the high power mode step size is approximately 220 na. the low power step size is approximately 5% lower than the ?111? setting. ?000? is the lowest power setting. ?111? is the highest power setting (30% power reduction). bits 1 to 0: eco_lp[1:0]. these bits set the gain mode. ?00? is the highest power setting. ?11? is the lowest power setting. (30% power reduction). for additional information, refer to the eco_trim register on page 270 . 9.3.3 eco_cfg register the eco configuration register provides status and control for the eco. bit 2 eco_lpm. this bit enables the eco low power mode when high. this is recommended for use only during sleep mode. bit 1 eco_exw. the eco exists written bit is used as a status bit to indicate that the eco ex bit was previously writ- ten to. it is read only. when this bit is a '1' indicates that the eco_cfg register was written to and is now locked. bit 0 eco_ex. the eco exists bit serves as a flag to the hardware, to indicate that an external crystal oscillator exists in the system. just after boot, it may be written only once to a value of '1' (crystal exists) or '0' (crystal does not exist). if the bit is '0', a switch-o ver to the eco is locked out by hardware. if the bit is '1', hardware allows the firmware to freely switch between the eco and ilo. it should be written as early as possible after a po wer on reset (por) or exter- nal reset (xres) event. for additional informa tion, refer to the eco_cfg register on page 277 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,d2h eco_enbus eco_enbus[2:0] rw : 07 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,d3h eco_trim eco_xgm[2:0] eco_lp[1:0] rw : 11 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,e1h eco_cfg eco_lpm eco_exw eco_ex rw : 00 [+] feedback
72 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c external crystal oscillator (eco) 9.3.4 related registers osc_cr0 register, on page 113 . prtxdr registers register on page 59 . prtxie registers register on page 59 . [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 73 10. sleep and watchdog this chapter discusses the sleep and watchdog operations and thei r associated registers. for a complete table of the sleep and watchdog registers, refer to the summary table of the core registers on page 24 . for a quick reference of all psoc reg- isters in address order, refer to the register reference chapter on page 187 . 10.1 architectural description device components that are involved in sleep and watchdog oper ation are the selected 32 khz clock, the wakeup timer, the sleep bit in the cpu_scr0 register, the sleep circuit (to sequ ence going into and coming out of sleep), the bandgap refresh circuit (to periodically refresh the reference voltage during sleep), and the watchdog timer . figure 10-1. sleep controller architecture outputs 32 khz clk control inputs osc_scr0 cpu_scr0 wakeup timer sleep control logic register decode logic (slp_cfg, slp_cfg2, slp_cfg3, internal configuration registers) sleep timer cpu hold off imo clk [+] feedback
74 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c sleep and watchdog 10.1.1 sleep control im plementation logic this section details the sleep mode logic implementation. conditions for entering the sleep modes: standby mode: set the sleep bit in the cp u_scr0 register. this asserts the "sle ep" signal for the sleep controller. i2c_usb mode: set the i2c_on bit in th e slp_cfg2 register and then set t he sleep bit in the cp u_scr0 register. another way to enter i2c_usb sleep mode is to set the usb enable bit in the usb_cr0 register and then set the sleep bit in the cpu_scr0 regi ster. this asserts the sl eep signal for the sleep controller and also the i2cenable signal to the power system. the i2c block works in i2c_usb sleep mode only to wake up the system. that is, when the device is in sleep, i2c can detect a start condition and receive an address. if the a ddress matches, i2c generates an interrupt and wakes the system (refer to power modes on page 141 ). if you put the device to sleep again while these transactions are ocurring (i.e., when you are in the middle of i2c transactions), i2c does not work and will send nacks. i2c can only detect a start condition and collect an 8-bit a ddress then wake the system throu gh an interrupt during i2c sleep mode. therefore it is recom- mended to check the bus status in the i2c_xstat register bef ore putting the device to sleep if there is any i2c data transfer. deep sleep mode: configure the i2c_on bit in the slp_cfg2 register to 0, then usb enable bit in the usb_cr0 regis- ter to '0' and the x32on bit in osc_cr0 to '0'. set the lso_ off bit in the slp_cfg2 regist er and then set the "sleep" bit in the cpu_scr0 register. this enables the lso_off signal to power down the lso. the system enters into deep sleep mode. one point to note here is to not set the x32on bit to '1' without sett ing the eco_ex (eco exists) bit in the eco_cfg (1,e1h) register to a '1'. if you do so, the deep slee p mode is not entered, but clk 32k is also not running. this implies that the sleep timer interrupt or th e programmable timer interrupt cannot occur. 10.1.1.1 wakeup logic waking up from standby mode is by an interrupt, which can be a sleep timer interrupt, a gpio interrupt, a 16-bit program- mable timer 0 interrupt, or a usb interrupt. for the device, the wakeup from i2c_usb sleep mode can be by an i2c interrupt in addition to a sleep timer interrupt, a programmable timer 0 interrupt, a gpio interrupt, or a usb interrupt. for the device, the wakeup from deep sleep mode ca n be by either a gpio interrupt or a usb interrupt. in standby mode during buzz, if the external supply falls below the lvd limit, an lvd interrupt occurs and initiates the wakeup sequence. in standby mode, if watchdog reset occurs, it first initiates th e wakeup sequence. once the wakeup is done, it resets the system. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 75 sleep and watchdog as shown in figure 10-2 , once the sleep bit is deasserted, the wakeup is initiated. the sequence is shown in the following timing diagram. the taps used in this wakeup sequence are generated based upon user conf iguration settings in the slp_cfg3 register.? figure 10-2. wakeup sequence for the device 123 1. the duration of power good is 3 ilo cycles. 2. the timing of t0 ? t4 is based on the imo frequency and the sett ings in the slp_cfg3 register. for additional information, re fer to the slp_cfg3 register on page 78 . 3. the maximum worst-case duration of the wakeup sequence is 26 3 s, based on the minimum specified ilo frequency of 19 khz, the minimum specified imo frequency, and the default settings of the slp_cfg3 register. power good int regulator enable power switches enable bandgap enable por enable imo enable t0 t1 t2 t3 interrupt sample bandgap switch reference from standby to bg sample por t4 brq sleep enable flash idle_flash ? cpu clock cycle pd 10 ? 60 s 3 ? 20 s 1 ? 20 s [+] feedback
76 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c sleep and watchdog note the t0, t1, and t2 mentioned in the slp_cfg3 reg- ister with respect to figure 10-2 on page 75 are defined as follows: t0: time duration between t0 and t1 in the timing dia- gram. t1: time duration between t1 and t2 in the timing dia- gram. t2: time duration between t3 and t4 in the timing dia- gram. 10.1.2 sleep timer the sleep timer is a 15-bit up counter clocked by the 32 khz clock source. this timer is always enabled except in deep sleep mode. the exception to this is within an ice ( in- circuit emulator ) in debugger mode and when the stop bit in the cpu_scr0 is set; the sleep timer is disabled, so that the user does not get continual watchdog resets when a breakpoint is hit in the debugger environment. if the associated sleep timer interrupt is enabled, a periodic interrupt to the cpu is gen erated based upon the sleep interval selected from the osc_cr0 register. the sleep timer functionality does not need to directly associate with the sleep state. it can be used as a general purpose timer interrupt regardless of sleep state. the reset state of the sleep timer is a count value of all zeros. there are two ways to reset the sleep timer. any hardware reset, (that is, po r, xres, or watchdog reset (wdr)) resets the sleep timer. there is also a method that allows the user to reset the sleep timer in firmware. a write of 38h to the res_wdt register clears the sleep timer. note any write to the res_wdt register also clears the watchdog timer. clearing the sleep timer is done at anytime to synchronize the sleep timer operation to cpu processing. a good exam- ple of this is after por. the cpu hold off, due to voltage ramp and others, may be signific ant. in addition, a signifi- cant amount of program initia lization may be required. how- ever, the sleep timer starts counting immediately after por and is at an arbitrary count when user code begins execu- tion. in this case, it is desirable to clear the sleep timer before enabling the sleep interrupt initially to ensure that the first sleep period is a full interval. 10.2 application overview the following are notes regarding sleep related to firmware and application issues. note 1 if an interrupt is pending, enabled, and scheduled to be taken at the instruction boundary after the write to the sleep bit, the system does not go to sleep. the instruction still executes, but it cannot set the sleep bit in the cpu_scr0 register. instead, the interrupt is taken and the effect of the sleep instruction ignored. note 2 there is no need to enable the global interrupt enable (cpu_f register) to wake the system out of sleep state. individual interrupt enables, as set in the interrupt mask registers, are sufficient . if the global interrupt enable is not set, the cpu does not service the isr associated with that interrupt. however, the system wakes up and continues executing instructions from the point at which it went to sleep. in this case, the user must manually clear the pending interrupt or subsequently enable the global interrupt enable bit and let the cpu take the isr. if a pending interrupt is not cleared, it is continuously asserted. although the sleep bit may be written and the sleep sequence executed as soon as the device enters sleep mode, the sleep bit is cleared by the pending interrupt and sleep mode is exited immediately. note 3 upon wakeup, the instruction immediately after the sleep instruction is executed be fore the interrupt service rou- tine (if enabled). the instruction after the sleep instruction is prefetched before the system actually goes to sleep. thus, when an interrupt occurs to wake the system up, the prefetched instruction executes and the interrupt service routine is executed. (if the global interrupt enable is not set, instruction execution continues where it left off before sleep.) note 4 if the global interrupt enable bit is disabled, it is safely enabled just before the instruction that writes the sleep bit. it is usually undesirable to get an interrupt on the instruction boundary just befor e writing the sleep bit. this means that upon return from the interrupt, the sleep com- mand is executed, possibly bypassing any firmware prepa- rations that are necessary to go to sleep. to prevent this, disable interrupts before making preparations. after sleep preparations, enable global interrupts and write the sleep bit with the two consecutive instructions as follows. and f,~01h // disable global interrupts // (prepare for sleep, could // be many instructions) or f,01h // enable global interrupts mov reg[ffh],08h // set the sleep bit because of the timing of the global interrupt enable instruc- tion, it is not possible for an interrupt to occur immediately after that instruction. the earli est for the interr upt to occur is after the next instruction (wri te to the sleep bit) is exe- cuted. if an interrupt is pending, the sleep instruction is exe- cuted; but as described in no te 1, the sleep instruction is ignored. the first instruction executed after the isr is the instruction after sleep. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 77 sleep and watchdog 10.3 register definitions the following registers are associated with sleep and watchdog operations and are listed in address order. each register description has an associated register table showing the bit stru cture for that register. the bits that are grayed out in the tables below are reserved bits and are not detailed in the regi ster descriptions. always write reserved bits with a value of ?0 ?. for a complete table of the sleep and watchdog registers, refer to the summary table of the core registers on page 24 . 10.3.1 res_wdt register the reset watchdog timer register (res_wdt) clears the watchdog timer (a write of any value) and clears both the watchdog timer and the sleep timer (a write of 38h). bits 7 to 0: wdsl_clear[7:0]. the watchdog timer (wdt) write-only register is designed to timeout at three sleep timer rollover events. if only the wdt is cleared, the next watchdog reset (wdr) occurs anywhere from two to three times the current sleep interval setting. if the sleep timer is near the beginning of its count, the watchdog time- out is closer to three times. however, if the sleep time r is very close to its terminal count , the watchdog timeout is closer to two times. to ensure a full three times timeout, clear both the wdt and the sleep timer. in applications that need a realtime clock and cannot reset the sleep timer when clearing the wdt, the duty cycle at which the wdt must be cleared is no greater than two times the sleep interval. for additional information, refer to the res_wdt register on page 253 . 10.3.2 slp_cfg register the sleep configuration regist er (slp_cfg) sets the sleep duty cycle. the value placed in this register is based upon factory test- ing. bits 7 and 6: pssdc[1:0]. the power system sleep duty cycle bits set the sleep duty cycle. for additional information, refer to the slp_cfg register on page 283 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,e3h res_wdt wdsl_clear[7:0] w : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,ebh slp_cfg pssdc[1:0] rw : 0 [+] feedback
78 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c sleep and watchdog 10.3.3 slp_cfg2 register the sleep configuration regi ster (slp_cfg2) holds the configuration for i2c sleep, deep sleep, and buzz. bits 3 and 2: alt_buzz[1:0]. these bits control additional selections for por/lvd buzz ra tes. these are lower rates than the compatibility mode to provide for lower average power. ?00? - compatibility mode, bu zz rate determined by pssdc bits. ?01? - duty cycle is 1/32768. ?10? - duty cycle is 1/8192. ?11? - reserved. bit 1: i2c_on. this bit enables the standby regulator in sleep at a level sufficient to supply the i2c circuitry. it is independent of the lso_off bit. bit 0: lso_off: this bit disables the lso oscillator when in sleep state. by default, th e lso oscillator runs in sleep. when this bit is ?0?, the standby regulator is active at a power level to supply the lso and sleep timer circuitry and the lso is enabled. when this bit is ?1?, the lso is disabled in sleep, which in turn, disables the sleep timer, watchdog timer, and por/lvd buzzing activity in sleep. if i2c_on is not enabled and this bit is set, the device is in the lowest power deep sleep mode. only a gpio interrupt awakens the device from deep sleep mode. for additional information, refer to the slp_cfg2 register on page 284 . 10.3.4 slp_cfg3 register the sleep configuration regi ster (slp_cfg3) holds the configuration of the wakeup sequence taps. it is strongly recommended to not alter this register set- ting . bit 6: dbl_taps. when this bit is set, all the tap values (t0, t1, and t2) are doubled for the wakeup sequence. bits 5 and 4: t2tap[1:0]. these bits control the duration of the t2-t4 sequence (see figure 10-2 on page 75 ) by selecting a tap from the wakeuptimer. note the t2 delay is only valid for the wakeup sequence. it is not used for the buzz sequence. ?00? - 1 s ?01? - 2 s ?10? - 5 s ?11? - 10 s bits 3 and 2: t1tap[1:0]. these bits control the duration of the t1-t2 sequence (see figure 10-2 on page 75 ) by select- ing a tap from the wakeup timer. ?00? - 3 s 01? - 4 s ?10? - 5 s ?11? - 10 s bits 1 and 0: t0tap[1:0]. these bits control the duration of the t0-t1 sequence (see figure 10-2 on page 75 ) by selecting a tap from the wakeup timer. ?00? - 10 s ?01? - 14 s ?10? - 20 s ?11? - 30 s for additional information, refer to the slp_cfg3 register on page 285 . 10.3.5 related registers int_msk0 register on page 51 . osc_cr0 register on page 113 . ilo_tr register on page 68 . cpu_scr0 register on page 138 . cpu_scr1 register on page 137 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,ech slp_cfg2 alt_buzz [1:0] i2c_on lso_off rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,edh slp_cfg3 dbl_taps t2tap [1:0] t1tap [1:0] t0tap [1:0] rw : 0x7f [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 79 sleep and watchdog 10.4 timing diagrams 10.4.1 sleep sequence the sleep bit in the cpu_scr0 register, is an input into the sleep logic circuit. this circuit is designed to sequence the device into and out of the hardware sleep state. the hardware sequence to put the device to sleep is shown in figure 10-3 and is defined as follows. 1. firmware sets the sleep bit in the cpu_scr0 register. the bus request (brq) signal to the cpu is immedi- ately asserted: this is a r equest by the system to halt cpu operation at an instruction boundary. 2. the cpu issues a bus request acknowledge (bra) on the following positive edge of the cpu clock. 3. the sleep logic waits for the following negative edge of the cpu clock and then asserts a system wide power down (pd) signal. in figure 10-3 , the cpu is halted and the system wide pd signal is asserted. the system wide pd signal co ntrols three major circuit blocks: the flash memory module, the internal main oscilla- tor (6/12 mhz oscillator that is also called the imo), and the bandgap voltage reference. these circuits transition into a zero power state. the only operational circuits on the device in standby sleep mode are the ilo, the bandgap refresh circuit, and the sup- ply voltage monitor circuit. in standby sleep mode the supply voltage monitor circuit is active only during the buzz interval. to properly detect and recover from a vdd brown out condi- tion, the configurable buzz rate must be frequent enough to capture the falling edge of vdd. if the falling edge of vdd is too sharp to be captured by the buzz rate, any of the follow- ing actions must be taken to en sure that the device properly responds to a brown out condition. bring the device out of sleep before powering down. this can be accomplished in firmware, or by asserting xres before powering down. assure that vdd falls below 100mv before powering back up. set the no buzz bit in the osc_cr0 register to keep the voltage monitoring circuit powered during sleep. increase the buzz rate to assure that the falling edge of vdd will be captured. the ra te is configured through the pssdc bits in the slp_cfg register. in deep sleep mode the ilo, bandgap refresh circuit and supply voltage monitor circuit are all powered down. how- ever, additional low-power voltage monitoring circuitry gets enabled when entering deep sleep. this additional low- power voltage monitoring circuitry allows vdd brown out conditions to be detected for edge rates slower than 1v/ms. figure 10-3. sleep sequence iow sleep brq bra pd on the falling edge of cpuclk, pd is asserted. the system clock is halted; the flash and bandgap are powered down. cpuclk firmware write to the sleep bit causes an immediate brq. cpu captures brq on next cpuclk edge. cpu responds with a bra. [+] feedback
80 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c sleep and watchdog 10.4.2 wakeup sequence after asleep, the only event that wakes the system is an interrupt. the global interrupt enable of the cpu flag regis- ter does not need to be set. any unmasked interrupt wakes the system up. it is optional for the cpu to actually take the interrupt after the wakeup sequence. the wakeup sequence is synchronized to the taps from the wakeup timer (running on imo clock). this allows the flash memory module enough time to power up before the cpu asserts the first read access. another reason for the delay is to allow the imo, bandgap, and lvd/por circuits time to settle before actually being used in the system. as shown in figure 10-2 , the wakeup sequence is as follows. 1. the wakeup interrupt occurs and the sequence is initi- ated at int (shown in figure 10-2 on page 75 ). the interrupt asynchronously enables the regulator, the bandgap circuit, lso, por, and the imo. as the core power ramps, the imo starts to oscillate and the remain- der of the sequence is timed with configurable durations from the wakeup timer. 2. at t1, the bandgap is sampled and the flash is enabled. 3. at t2, the flash is put in power saving mode (idle). 4. at t3, the por/lvd comparators are sampled and the cpu restarts. there is no difference in wakeup from deep sleep or buzzed sleep because in all cases, in order to achieve the power specification, the r egulator, references and core blocks must be shut off. 10.4.3 bandgap refresh during normal operation the bandgap circuit provides a volt- age reference (vref) to the system for use in the analog blocks, flash, and low voltage detect (lvd) circuitry. nor- mally, the bandgap output is connected directly to the vref signal. however, during sleep, the bandgap reference gen- erator block and lvd circuits are completely powered down. the bandgap and lvd blocks are periodically reenabled during sleep to monitor for low voltage conditions. this is accomplished by periodically turning on the bandgap. the rate at which the refresh occurs is related to the 32 khz clock and controlled by the power system sleep duty cycle. table 10-1 lists the available selections. figure 10-4. buzz sequence timing the buzz sequence after the buzz si gnal comes. this is shown in figure 10-4, ?buzz sequence timing,? on page 80 . table 10-1. power system sleep duty cycle selections pssdc sleep timer counts period (nominal) 00b (default) 256 8 ms 01b 1024 31.2 ms 10b 64 2 ms 11b 16 500 s note valid when alt_buzz[1:0] of the slp_cfg2 register is 00b. power good buzz regulator enable r switches enable bandgap enable por enable imo enable t0 t1 t2 t3 buzz sample bandgap switch reference om standby to bg sample por t4 2 imo cycles 10-30 us 3-10 us 1-10 us [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 81 sleep and watchdog 10.4.4 watchdog timer on device boot up, the watchdog timer (wdt) is initially disabled. the pors bit in the system control register con- trols the enabling of the wdt. upon boot, the pors bit is initially set to '1', indicating that either a por or xres event occurred. the wdt is enabled by clearing the pors bit. after this bit is cleared and the wdt enabled, it cannot be disabled. (the pors bit cannot be set to '1' in firmware; only cleared.) the only way to disable the watchdog function after it is enabled is through a subsequent por or xres. even though the wdt is disabled during the first time through ini- tialization code after a por or xres, write all code as if it is enabled (that is, periodically review the wdt). this is because in the initialization code after a wdr event, the watchdog timer is enabled so all code must be aware of this. the watchdog timer is three counts of the sleep timer inter- rupt output. the watchdog interval is three times the selected sleep timer interval. the available selections for the watchdog interval are shown in ta b l e 1 0 - 1 . when the sleep timer interrupt is asserted, the watchdog timer increments. when the counter reaches three, a terminal count is asserted. this terminal count is registered by the 32 khz clock. therefore, the wdr (watchdog reset) signal goes high after the falling edge of the 32 khz clock and held asserted for one cycle (30 s nominal). the flip-flop that registers the wdt terminal count is not reset by the wdr signal when it is asserted, but is reset by all other resets. this timing is shown in figure 10-5 . figure 10-5. watchdog reset after enabled, periodically clear the wdt in firmware. do this with a write to the res_wdt register. this write is data independent, so any write clears the watchdog timer. (note that a write of 38h also clears the sleep timer.) if for any rea- son the firmware fails to clear the wdt within the selected interval, the circuit asserts wdr to the device. wdr is equivalent in effect to any other reset. all internal registers are set to their reset state. (see the table titled reset func- tionality on page 141 .) an important aspect to remember about wdt resets is that ram initialization can be disabled (iramdis is in the cpu_scr1 register). in this case, the sram contents are unaffected; so that when a wdr occurs, program variables are persistent through this reset. in practical application, it is important to know that the watchdog timer interval can be anywhere between two and three times the sleep timer interval. the only way to guaran- tee that the wdt interval is a full three times that of the sleep interval is to clear the sleep timer (write 38h) when clearing the wdt register. however, this is not possible in applications that use the sleep timer as a realtime clock. in the case where firmware clears the wdt register without clearing the sleep timer, this occurs at any point in a given sleep timer interval. if it occurs just before the terminal count of a sleep timer interval, the resulting wdt interval is just over two times that of the sleep timer interval. sleep int wd reset (wdr) clk32k 2 wd count 3 0 [+] feedback
82 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c sleep and watchdog [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 83 section c: truetouch system the configurable truetouch? system section discusses the truetouch and analog components of the psoc device and the registers associated with those components. th is section encompasses the following chapters: truetouch module on page 85 . i/o analog multiplexer on page 99 . comparators on page 101 . top-level truetouch architecture the figure below displays the top level ar chitecture of the psoc?s tr uetouch system. each compo nent of the figure is dis- cussed at length in this section. psoc truetouch system truetouch system analog reference truetouch module system bus global analog interconnect analog mux two comparators [+] feedback
84 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section c: truetouch system truetouch register summary the table below lists all the psoc registers for the truetouch s ystem in address order within their system resource configura- tion. the bits that are grayed out are reserved bits. if thes e bits are written, always write them with a value of ?0?. summary table of the truetouch registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access truetouch module registers (page 92 ) 0,a0h cs_cr0 csout[1:0] csd_ prsclk csd_cs_ clk csd_ mode mode[1:0] en rw : 00 0,a1h cs_cr1 chain clksel[1:0] rloclk inv insel[2:0] rw : 00 0,a2h cs_cr2 irange idacdir idac_en cin_en pxd_en cip_en ro_en rw : 00 0,a3h cs_cr3 refmux refmode ref_en lpfilt[1:0] lpf_en[1:0] rw : 00 0,a4h cs_cntl data[7:0] ro : 00 0,a5h cs_cnth data[7:0] ro : 00 0,a6h cs_stat ins cols cohs pps inm colm cohm ppm # : 00 0,a7h cs_timer timer count value[6:0] rw : 00 0,a8h cs_slew fastslew[6:0] fs_en rw : 00 0,a9h prs_cr cs_clk_ou t cs_clk_in v prs_12bit prs_en prescale_ byp prescale_clk_div[2:0] rw : 00 0,fdh idac_d dacdata[7:0] rw : 00 io analog multiplexer registers (page 100 ) 0,61h amux_cfg prx_ mode icapen[1:0] intcap[1:0] rw : 00 1,d8h mux_cr0 enable[7:0] rw : 00 1,d9h mux_cr1 enable[7:0] rw : 00 1,dah mux_cr2 enable[7:0] rw : 00 1,dbh mux_cr3 enable[7:0] rw : 00 1,dfh mux_cr4 enable[3:0] rw : 0 comparator registers (page 103 ) 0,78h cmp_rdc cmp1d cmp0d cmp1l cmp0l # : 0 0,79h cmp_mux inp1[1:0] inn1[1:0] inp0[1:0] inn0[1:0] rw : 00 0,7ah cmp_cr0 cmp1en cmp0en rw : 0 0,7bh cmp_cr1 cint1 cpin1 crst1 cds1 cint0 cpin0 crst0 cds0 rw : 00 0,7ch cmp_lut lut1[3:0] lut0[3:0] rw : 00 legend # access is bit specific. refer to the register reference chapter on page 187 for additional information. r read register or bit(s). w write register or bit(s). [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 85 11. truetouch module this chapter presents the truetouch module and its associated registers. for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 11.1 architectural description 11.1.1 types of truetouch approaches a block diagram of the overall capacitive sensing architec- ture is shown in figure 11-1 . cs1 through csn are the capacitors being measured. the various sensing approaches use different subsets of this hardware. figure 11-1. truetouch module block diagram 11.1.1.1 positive charge integration in the positive charge integration method, charge on a sense capacitor is integrated onto a larger capacitor, starting from ground. the number of cycles required to reach a tar- get voltage gives a measurement of the sensed capaci- tance. the hardware configuration for this approach is shown in figure 11-2 . the hardware supports the use of either pin p0[1] or p0[3] for the external integration capaci- tor. figure 11-2. positive charge integration block diagram idac reference buffer vr c external c internal analog global bus truetouch counters comparator mux mux refs relaxation oscillator (ro) csclk imo + - truetouch clock select cs1 cs2 csn reference buffer vr analog global bus truetouch logic comparator mux mux refs truetouch clock select pin enables csclk csclk imo csclk 16-bit counter c external p0[1] or p0[3] s cs1 cs2 csn [+] feedback
86 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c truetouch module the circuit operates by alternately charging the sense capacitance to the internal voltage buffer level (first phase), then on the opposite phase of the clock (second phase), the analog global bus is connected to the integration capacitor while the voltage buffer is disconnected. (see figure 11-3 .) this builds up voltage on the integration capacitor, and eventually it trips the monitoring comparator. the compara- tor is configured to capture the number of counts of the inter- nal oscillator during the charging interval, yielding a capacitance measurement of the sense pin. figure 11-3. charging the truetouch and connection 11.1.1.2 relaxation oscillator the relaxation oscillator (ro) method operates by forming an oscillator using the sense capacitance. the idac, sense capacitance, and comparator (switching between two refer- ences) form the ro. there are two ro methods of capsens- ing supported. in the first method, the ro is compared to the frequency of a similar internal oscillator. normally, the relaxation oscillator is initially tuned (through firmware) to match the internal oscillator or to match a submulti ple of the inte rnal oscillator. the frequency difference is measured by defining an interval of internal oscillator clo cks and counting th e number of ro periods that occur during this interval. (see figure 11-4 .) two 8-bit counters are used: one clocked by the internal oscillator and one clocked by the relaxation oscillator. with the ro frequency closely matched to the internal oscil- lator and the interval set to 256 clocks, the 8-bit ro count result is the difference between the two oscillators. an over- flow bit is available to test whether the number of capture counts is greater than or less than 256. other count intervals are available. (see figure 11-13 .) figure 11-4. relaxation oscillator #1 block diagram in the second ro method, the interval is set by a number of cycles of the ro using a 6-bit counter. during this interval, the imo clocks a 16-bit counte r and the final count gives a measure of capacitance. (see figure 11-5 .) reference buffer vr c external p0[1] or p0[3] analog global bus comparator mux mux vref closed closed reference buffer vr analog global bus comparator mux mux vref closed open closed open first phase: charging the sense capacitor cs1 second phase: integrating charge onto integration capacitor csclk pin enables csclk c external p0[1] or p0[3] pin enables csclk csclk cs1 cs2 csn cs1 cs2 csn idac analog global bus comparator mux mux refs truetouch clock select ro clock imo csclk pin enables truetouch logic 8-bit counter 8-bit counter cs1 cs2 csn [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 87 truetouch module figure 11-5. relaxation oscillator #2 block diagram 11.1.1.3 successive approximation the successive approximation method provides a fast algo- rithm for capacitance measurement for applications such as detecting button presses. after a baseline is established, a set of capacitive sensors are very quickly scanned. high sensitivity can be achieved to enable scanning through a large dielectric. figure 11-6 shows the hardware used in this method. the successive approximation method is used for proximity detection, fast button detection, and high resolu- tion capacitance change measurement. the truetouch successive approximation (csa) user module in psoc designer? uses this method. in this method, an internal capacitor is connected to the ana- log global bus. this bus contains ripple at the clock fre- quency, which is filtered with a low pass filter leading into the comparator. in addition, the idac current is set to the desired value as explained later in this section. figure 11-6. successive approximation block diagram the reference bus is connected to the analog global line to initialize it to the vr voltage (see figure 11-7 ). after that, the reference buffer is disconnected and not used. the sense capacitance pin is now alternately grounded (see figure 11-8 ) and connected to the analog global (see figure 11-9 ). with the idac?s current driving onto this net, the global net alternately charges and discharges a small amount. figure 11-7. initialization phase for successive approximation analog global bus comparator mux mux refs truetouch clock select ro clock imo csclk pin enables truetouch logic 6-bit counter 16-bit counter idac cs1 cs2 csn idac analog global bus vr lp filter closed csclk ref_en truetouch clock select imo csclk comparator mux mux m8c read reference buffer vr cs1 cs2 csn c internal vr idac reference buffer analog global bus vr lp filter closed closed comparator mux mux m8c read c internal cs1 cs2 csn [+] feedback
88 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c truetouch module for typical capacitances, the idac current can be config- ured so that the average voltage on the analog global does not change. this can be done in firmware using a succes- sive approximation to find the idac setting that causes the global net to remain relatively stable for the load capaci- tance. after this baseline is set, a small increase in sense capacitance causes the global net to slowly discharge, eventually crossing the comparator threshold. the config- urable low pass filter is designed to filter the ripple on the global net, leaving the average voltage that indicates capac- itance change. firmware can read the comparator state after a pre-selected time to see if a large enough change has occurred to trip the comparator in that time. this approach is well suited to quickly detecti ng a capacitive button press. alternately, capacitance can be accurately measured by going through the complete successive approximation pro- cedure. the final idac setting gives a measurement of capacitance. the delay between starting the pin switching and reading the comparator can be set by a firmware delay, or by using the 6-bit counter in the truetouch logic to generate an inter- rupt. figure 11-8. first phase of successive approximation figure 11-9. second phase of successive approximation 11.1.1.4 negative charge integration the negative charge integration method operates by initial- izing an integration capacitor to a positive voltage, then dis- connecting this driver. the integration capacitor voltage decays through connection with an external sense capacitor that is continuously switched between ground and the inte- gration capacitor. the number of cycles required to reduce the voltage on the integration capacitor to a target value gives a measure of the sense capacitance. see figure 11-10 . the hardware supports the use of either pin p0[1] or p0[3] for the external integration capacitor. vr idac reference buffer analog global bus comparator mux mux vr lp filter closed m8c read i out conn. to ground csclk c internal cs1 cs2 csn reference buffer analog global bus comparator mux mux vr lp filter closed m8c read conn. to bus csclk vr idac i out c internal cs1 cs2 csn [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 89 truetouch module figure 11-10. negative charge integration block diagram the initialization phase for negative ci (charge integration) is the same as for su ccessive approximation ( figure 11-7 ). following that, a two-phase sequence discharges the inte- gration capacitor, as illustrated in figure 11-11 and figure 11-12 . figure 11-11. negative charge integration first phase: grounding the sense capacitor figure 11-12. negative charge integration second phase: integrating charge onto integration capacitor 11.1.1.5 sigma delta the sigma delta capacitive sensing operates by holding an integration capacitor voltage near a target threshold, and charging the voltage up or down based on the present state of a comparator output. the sense capacitor is continuously switched between ground and the integration capacitor, which drives the integrated voltage down on each switching cycle. when the integr ation voltage is below the reference threshold, a current from the internal idac is used to charge the capacitor above the threshold again. the truetouch sigma delta (csd) user module in psoc designer uses this method. as the integration capacitor voltage moves back and forth across the comparator threshold, the comparator "high" out- puts are counted in an interval to give a measure of the sense capacitor. the larger the sense capacitor, the more time the comparator is low, and so the count is less. to reduce noise, the sense capacitor is driven with a pseudo-random sequence (prs). an 8- or 12-bit sequence can be selected, and the prs is clocked from a prescaler giving input rates of the main system clock or any divide-by- two of this, down to sysclk/256. the counter accumulates counts for a selected interval, typicall y the cycle length of the prs (511 or 1023 cycles of the prs prescale clock). when bit 0 (en) and bit 3 (csd_mode) of the cs_cr0 register are set to ?1?, the truetouch counters are enabled to work in csd mode. when both cmp0 (this input is double synchronized) and the "start" signal from programmable timer are ?1?, the counters increment. when this comparator output is low, the counters hold their count until the compar- ator goes high again. in this case: reference buffer vr s analog global bus truetouch logic comparator mux mux refs truetouch clock select csclk and pin enables ref_en imo csclk closed 16-bit counter c external p0[1] or p0[3] cs1 cs2 csn reference buffer vr cs1 cs2 csn analog global bus comparator mu x mu x vr e f grounded open closed c external c internal reference buffer vr cs1 cs2 csn analog global bus comparator mu x mu x vre f closed closed open c extern a c internal [+] feedback
90 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c truetouch module a. if the start output from the timer1 is still ?1? - counters start incrementing again. b. if the start is ?0? (start can become zero before comparator becomes ?1? again) - counters stop tog- gling. to start a new count, the en bit in the cs_cr0 register must be disabled and enabled again. following is a typical capacitance measurement algorithm: select clock prescale (imo di vide by 1, 2, 4, ? 256). configure the prs (8 or 12 bits) and let it free-run. connect external modulation capacitor (cmod) to the analog global bus. initialize cmod with the reference buffer, to vref. enable the sense capacitor, which now switches at the prs rate. enable the idac / comparator / truetouch counter sys- tem, set the interval timer's count. at this point, the analog global bus voltage moves back and forth around the vref threshold. enable the interval timer to start accumulating counts for the selected interval. when the interval ends (for example, with an interrupt), the counter holds a count related to capacitance. 11.1.2 idac the internal current dac provides a bias current for use with the relaxation oscillator (ro) or for capacitance mea- surement in successive approximation mode. it can also be set to supply a sinking or sourcing current to any i/o pin through the analog global bus connection. the idac current is set by the 8-bit idac_d register. in addition, the two irange bits in the cs_cr2 register pro- vide additional prescaling range. 11.1.3 truetouch counter the truetouch counter block (see figure 11-13 ) is opti- mized to implement both the charge integration algorithm and the relaxation oscillator algorithms. the hardware con- sists of two 8-bit up-counters with capture that can be optionally chained into a single 16-bit capture counter and an additional 6-bit counter. in the charge integration algorithms, a single comparator channel is an input to the count-enable logic of a 16-bit cap- ture counter. in this implementation, the counters are chained to create the higher resolution required. when dis- abled, the counter is reset; when the enable bit (en bit in cs_cr0) is written to a ?1?, the counter operation starts and a subsequent comparator trip asserts the capture input. this algorithm can be operated continuously or in one shot mode. in one shot mode, the capture event causes the counters to freeze. the host processor then reads the cur- rent count. select the block interrupt from either the input capture or the 16-bit overflow. in the first relaxation algorithm, the 8-bit counters operate separately. one of the counters is clocked by csclk, a divided version of the internal main oscillator (imo), and one is clocked by the relaxation oscillator (ro) formed by the truetouch system. in this configuration, the counters are enabled simultaneously with a write to the enable bit. upon terminal count of counter low, the contents of counter high are captured. use the value of the counter high capture to compute the difference between ro and imo frequency. changes in this count then indicate capacitance changes. in the second relaxation algorithm, a 6-bit counter is clocked by the relaxation oscillator. a 16-bit chained counter is formed and clocked by csclk, a divided version of the internal main oscilla tor (imo). in this configuration, the counters are enabled simultaneously with a write to the enable bit. upon terminal count of the 6-bit ro counter, the contents of the 16-bit counter are captured. changes in this count then indicate capacitance changes. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 91 truetouch module figure 11-13. truetouch counter block diagram the programmable timer is a 6-bit down counter with a ter- minal count output. this timer has one data register associ- ated with it. the timer is started when the truetouch block is enabled. the enable signal is double synchronized to the timer?s clock domain. when started, the timer always starts counting down from the value loaded into its data registers (cs_timer). this timer only has a one shot mode, in which the timer completes one full count cycle and stops. disabling and reenabling the truetouch block restarts the timer. figure 11-14. rlo timer block diagram the timer?s clock is either the 32 khz clock (rlo) or the truetouch count clock, depending upon the value of the pxd_en bit in the cs_cr2 register. see the cs_cr2 reg- ister on page 93 for details. 11.1.3.1 operation when started, the timer loads the value contained in its data register and counts down to its terminal count of zero. the timer outputs an active high terminal count pulse for one clock cycle when it reaches the terminal count. the low time of the terminal count pulse is equal to the loaded decimal count value multiplied by the clock period. (tc pw = count value decimal * clk period ). the period of the terminal count output is the pulse width of the terminal count plus one clock period (tc period = tc pw + clk period ). refer to the timing dia- gram in figure 11-19 on page 98 . 8-bit up counter low byte counter high byte counter 0 1 2 3 0 1 csclk rlo clksel[1:0] rloclock chain co 8-bit up counter col 0 1 2 3 csout[1:0] insel[2:0] imo inm ins r s colm cols r s col colr i n cohm cohs r s coh cohr ppm pps r s pf done (control logic) cs_int to pin coh count_en co imo imo/2 imo/4 imo/8 cs_int in colr cohr reset yes mode=00 or 11 count_en=0 pf_done=0 mode=01 or 10 yes count_en=1 block enabled ? falling edge? rising edge? inter- rupt mode=00 mode=11 mode=01 mode=10 no yes no no yes yes count_en=0 pf_done=1 rising edge? no block enable d? no clk clk/rlo imo count_en no yes count_en=0 inv 0 1 2 3 4 5 6 7 edge detect cmp0 ilo cmp1 rlo_timer_tc timer rlo_timer_irq muxbus ?0? 6-bit counter rlo_timer_tc rlo_timer_irq co iow or block_en iow or block_en iow or block_en iow or block_en 0 1 csclk pxd_en rlo register relaxation oscillator programmable timer data[5:0] terminal count irq truetouch clock [+] feedback
92 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c truetouch module 11.2 register definitions the following registers are associated with the truetouch modul e and are listed in address order. the register descriptions have an associated register table showing the bit structure for that register. the bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions th at follow. always write reserved bits with a value of ?0?. fo r a complete table of truetouch module registers, refer to the truetouch register summary on page 84 . 11.2.1 cs_cr0 register the truetouch control register 0 (cs_cr0) controls the operation of the truetouch counters. do not write bits [7:1] while the block is enabled. bits 7 and 6: csout[1:0]. these bits select between a number of truetouch signals that can be driven to an output pin. refer to figure 11-13 on page 91 and to the out_p1 register on page 273 . bit 5: csd_prsclk. this bit selects between imo-p or the prs output as a clock source to drive the main capacitor switch. ?0? selects imo-p. ?1? selects prs output. bit 4: csd_cs_clk. this bit selects between imo or imo-p for the truetouch counters to work. depending on this bit selection, either imo or imo-p is sent as the source clock to the clock dividers, which generate cs_clk as shown in figure 11-13 on page 91 . ?0? selects imo. ?1? selects imo-p. bit 3: csd_mode. this bit enables the csd mode. when this bit is enabled, the timer1 block works on the imo-p (pre-scaled imo) clock. this is also an enable for truetouch counters to toggle. ?0? disables csd mode. programmable timer1 works on either cpuclk/clk32, (de pending on clksel bit selec- tion in the pt1_cfg (0, b3h) register). ?1? enables csd mode. when this bit is set to ?1?, the programmable timer1 works on imo-p. note : once the csd_mode bit is enabled, the imo-p clock is a free running divider clock that cannot be stopped and re- started. the imo-p and the cpu clock are both derived from the imo clock but the phase relationship between them is nondeterministic. bits 2 and 1: mode[1:0]. these bits specify the operating mode of the counter logic. the modes are shown in the fol- lowing table. bit 0: en. when this bit is written to ?1?, the counters are enabled for counting. when this bit is written to ?0?, counting is stopped and all counter values are reset to zero. if the counting mode is stopped in conjunction with an event (see mode[1:0]), the current count is held and read from the counter registers. toggle the en bit to ?0? and then back to ?1? to start a new count. for additional information, refer to the cs_cr0 register on page 211 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a0h cs_cr0 csout[1:0] csd_ prsclk csd_cs_ clk csd_ mode mode[1:0] en rw : 00 csout[1:0] description 00 in 01 cs_int 10 col 11 coh mode[1:0] description 00 stop on event in this mode, the block starts counting when the en bit is set, and stops counting upon the selected interrupt event. this mode allows the user to read the counter results in firmware. counting is restarted again by disabling and re- enabling the block using the en bit. 01 pulse width in this mode, after the en bit is set, the block waits for a positive edge upon the data input selection to start the counter, and then stops the counter upon the following neg- ative edge of the data input. polarity is adjusted with the inv bit (cs_cr1). counting is restarted by disabling and re-enabling the block using the en bit. 10 period in this mode, after the en bit is set, the block waits for a positive edge upon the data input selection to start the counter, and then stops the counter upon the following pos- itive edge of the data input. polarity is adjusted with the inv bit (cs_cr1). counting is restarted by disabling and re- enabling the block using the en bit. 11 continuous in this mode, the counter is used to generate a periodic interrupt. the period is set by the input clock selection in conjunction with using one 8-bit counter (period=100h) or the chained 16-bit counter (period = 10000h). [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 93 truetouch module 11.2.2 cs_cr1 register the truetouch control register 1 (cs_cr1) contains addi- tional truetouch system control options. never write to this register while the block is enabled. bit 7: chain. when this bit is a ?0?, the two 8-bit counters operate independently. when this bit is a ?1?, the counters are chained to operate as a 16-bit counter. bits 6 and 5: clksel[1:0]. these bits select the true- touch module frequency of operation according to the fol- lowing table: bit 4: rloclk. when this bit is a ?0?, the entire truetouch system runs at the frequency specified in the clksel[1:0] bits. when this bit is a ?1?, the high counter is clocked inde- pendently by the truetouch rlo clock. bit 3: inv. input invert. when this bit is a ?0?, the input polarity is unchanged. when this bit is a ?1?, the data input select is inverted. bits 2 to 0: insel[2:0]. input selection. these bits control the selection of input signals for event control according to the following table: for additional information, refer to the cs_cr1 register on page 212 . 11.2.3 cs_cr2 register the truetouch control register 2 (cs_cr2) contains addi- tional truetouch system control options. bits 7 and 6: irange. these bits scale the idac current output. bit 5: idacdir. this bit determines whether the idac sinks or sources current to the analog global bus when enabled. bit 4: idac_en. this bit enables manual connection of the idac to the analog global bus. bit 3: cin_en. this bit enables the negative charge inte- gration capacitor sense approach. this causes the selected sense pin to alternately connect to the analog global bus and ground, at the rate select ed by the clksel bits in the cs_cr1 register. bit 2: pxd_en. this bit drives a clock to each i/o pin that is enabled for connection to the analog global bus. this clock alternately connects the pin to the bus, then connects the pin to ground. the clock rate is selected by the clksel bits in the cs_cr1 register. in addition, the idac sources current to the bus. the programmable timer is clocked by this same clock. bit 1: cip_en. this bit enables the positive charge integra- tion capacitor sense approach. this causes the reference buffer and the selected integration capacitor pin(s) to alter- nately connect to the analog global bus at the rate selected by the clksel bits in the cs_cr1 register. bit 0: ro_en. this bit enables the relaxation oscillator. the internal ro is connected to the analog global bus, and the capacitance of any connected pins affects the ro fre- quency. the oscillator current is set by the value of the idac_d register. for additional information, refer to the cs_cr2 register on page 213 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a1h cs_cr1 chain clksel[1:0] rloclk inv insel[2:0] rw : 00 clksel[1:0] frequency of operation 00 imo 01 imo/2 10 imo/4 11 imo/8 insel[1:0] selected input 000 comparator 0 001 ilo 010 comparator 1 011 rlo timer terminal count 100 internal timer 101 rlo timer irq 110 analog global mux bus 111 ?0? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a2h cs_cr2 irange idacdir idac_en cin_en pxd_en cip_en ro_en rw : 00 [+] feedback
94 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c truetouch module 11.2.4 cs_cr3 register the truetouch control register 3 (cs_cr3) contains con- trol bits primarily for the low pass filter and reference buffer. bit 6: refmux. this bit selects between vref and refhi for the reference buffer input. bit 5: refmode. this bit is used for manual connection of the reference buffer to the analog global bus. if either the ci_en or ro_en bits are set high in the cs_cr2 register, this bit has no effect. bit 4: ref_en. this bit enables the reference buffer to drive to the analog global bus. bits 3 and 2: lpfilt[1:0]. these bits control the time con- stant of the low pass filter that connect to the analog bus. bits 1 and 0: lpf_en[1:0]. these bits are used to connect a low pass filter into the input of either comparator channel. for additional information, refer to the cs_cr3 register on page 214 . 11.2.5 cs_cntl register the truetouch counter low byte register (cs_cntl) con- tains the current count for the low byte counter. bits 7 to 0: data[7:0]. this value contains the current count for the counter low block. stop this block to read a valid value. for additional information, refer to the cs_cntl register on page 215 . 11.2.6 cs_cnth register the truetouch counter high byte register (cs_cnth) contains the current count value for the high byte counter. bits 7 to 0: data[7:0]. this value contains the current count for the counter high block. stop this block to read a valid value. for additional information, refer to the cs_cnth register on page 216 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a3h cs_cr3 refmux refmode ref_en lpfilt[1:0] lpf_en[1:0] rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a4h cs_cntl data[7:0] ro : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a5h cs_cnth data[7:0] ro : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 95 truetouch module 11.2.7 cs_stat register the truetouch status register (cs_stat) controls true- touch counter options. status bits 7 to 4. the posted truetouch interrupts are the corresponding status bits in this register. interrupt clearing is performed by clearing the associated status bit. status can only be updated while the block is enabled and running. all status bits are cleared when the block is disabled. bit 7: ins. input status. reading a ?1? indicates a rising edge on the selected input was detected. reading a ?0? indi- cates that this event did not occur. this bit is cleared by writ- ing a ?0? to this bit position. writing a ?1? has no effect. bit 6: cols. counter carry out low status. reading a ?1? indicates an overflow occurred in the counter low block. reading a ?0? indicates that this event did not occur. this bit is cleared by writing a ?0? to th is bit position. writing a ?1? has no effect. bit 5: cohs. counter carry out high status. reading a ?1? indicates an overflow occurred in the counter high block. reading a ?0? indicates that this event did not occur. this bit is cleared by writing a ?0? to th is bit position. writing a ?1? has no effect. bit 4: pps. pulse width/period status. reading a ?1? indi- cates the completion of a pulse width or period measure- ment (as defined by the mode[1:0] bits in cs_cr0). this bit is cleared by writing a ?0? to this bit position. writing a ?1? has no effect. mask bits 3 to 0. never modify the interrupt mask bits while the block is enabled. if modification to bits 3 to 0 is necessary while the block is enabled, make certain that the status bits, bits 7 to 4, are not accidentally cleared. do this by writing a ?1? to all of the status bits when writing to the mask bits. bit 3: inm. input interrupt mask. when this bit is a ?1?, a ris- ing edge event on the input asserts the block interrupt. when this bit is a ?0?, this event is masked. bit 2: colm. counter carry out low mask. when this bit is a ?1?, a carry out from the counter low block asserts the block interrupt. when this bit is a ?0?, this event is masked. bit 1: cohm. counter carry out high mask. when this bit is a ?1?, a carry out from the counter high block asserts the block interrupt. when this bit is a ?0?, this event is masked. bit 0: ppm. pulse width/period mask. when this bit is a ?1?, the completion of a pulse width or period measurement asserts the block interrupt. when this bit is a ?0?, this event is masked. for additional information, refer to the cs_stat register on page 217 . 11.2.8 cs_timer register the truetouch timer register (cs_timer) sets the timer count value. bits 6 to 0: timer count value[6:0]. the 6-bit value in this register sets the initial count value for the timer. for additional information, refer to the cs_timer register on page 218 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a6h cs_stat ins cols cohs pps inm colm cohm ppm # : 00 legend # access is bit specific. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a7h cs_timer timer count value[6:0] rw : 00 [+] feedback
96 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c truetouch module 11.2.9 cs_slew register the truetouch slew control register (cs_slew) enables and controls a fast slewing mode for the relaxation oscillator. bits 7 to 1: fastslew[6:0]. this 7-bit count sets the time interval, in imo cycles, for a fa ster slew rate on the relax- ation oscillator edges. the interval applies to both rising and falling edges. this timer value has no effect unless the fs_en bit is set high. bit 0: fs_en. this bit enables the fast slewing interval on each edge of the relaxation oscillator. for additional information, refer to the cs_slew register on page 219 . 11.2.10 prs_cr register pseudo random sequence and prescaler control register controls the prescaler and pseudo random sequence gen- erator output. bit 7: cs_clk_out. this bit selects the truetouch clock (inversion or non-inversion depending on bit 6 setting) to be routed onto primary pin depending on the out_p1/out_p0 register selection. use a '1' to route prescaler output or prs output (depending on the csd_prsclk in cs_cr0 when in csd mode) or route the clock based on clksel bits in the cs_cr1 regis- ter in normal truetouch mode to primary pins p1[2]/p0[7] (depending on out_p1/out_p0 bit selections instead of the normal csout[1:0] selections). see the out_p1/ out_p0 registers for more details. use a '0' to use csout [1:0] selections as normal. bit 6: cs_clk_inv. this bit allows you to selectively route either the truetouch clock or the inversion of the truetouch clock onto a pin. a '1' routes inverted truetouch clock to pin (see bit 7). a '0' routes non-inverted truetouch clock to pin (see bit 7). bit 5: prs_12bit. this bit allows selection between 8-bit prs or 12-bit prs output. with '0', the msb of the 8-bit prs is sent out. with '1', the msb of the 12-bit pr s is sent out. bit 4: prs_en. this bit is used to enable or disable the prs block. with '0', the prs is disabled. the prs block output is 0. with '1', the prs is enabled and bit 5 decides whether the msb of the 12-bit prs is sent out or the msb of the 8-bit prs is sent out. bit 3: prescale_byp. this bit is used to bypass the prescaler and pass the input clock undivided onto the out- put. the output of the prescaler feeds the clock input to the prs block. with '0', the divided clock is sent out of the pres- caler depending on the setting of bit [2:0]. with '1', the incoming imo clock is sent out of the prescaler without any division. bits 2 to 0: prescale_clk_div[2:0]. these bits allow the selection of one of eight frequencies of the incoming imo clock to be fed as input to the prs block. for additional information, refer to the prs_cr register on page 220 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a8h cs_slew fastslew[6:0] fs_en rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,a9h prs_cr cs_clk_out cs_clk_inv prs_12bit prs_en prescale _byp prescale_clk_div[2:0] rw : 00 prescale_clk_div[2:0] description 000 divides the input imo clock by 2 001 divides the input imo clock by 4 010 divides the input imo clock by 8 011 divides the input imo clock by 16 100 divides the input imo clock by 32 101 divides the input imo clock by 64 110 divides the input imo clock by 128 111 divides the input imo clock by 256 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 97 truetouch module 11.2.11 idac_d register the current dac data register (idac_d) specifies the 8- bit multiplying factor that determines the output dac cur- rent. bits 7 to 0: idacdata[7:0]. the 8-bit value in this register sets the current driven onto the analog global mux bus when the current dac mode is enabled. for additional information, refer to the idac_d register on page 256 . 11.3 timing diagrams figure 11-15. event timing (mode = 00) figure 11-16. pulse width frequency timing (mode = 01/10) figure 11-17. continuous timing (mode = 11) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,fdh idac_d idacdata[7:0] rw : 00 sysclk block enable count enable event count 00 01 02 03 88 87 89 04 sysclk block enable edge detect count enable count 00 01 02 95 94 96 03 input signal sysclk block enable count enable count 00 01 02 45 44 00 03 [+] feedback
98 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c truetouch module figure 11-18. high byte counter timing (rlo clock selected) figure 11-19. 6-bit rlo timer operation sysclk low byte count enable high byte count enable high byte count low byte count 00 01 low byte clock 02 03 04 high byte clock 01 02 00 rlo clock en synchronized en 00h 00h 03h 02h 01h count rlo_timer_tc rlo_timer_irq cs_timer[5:0] 03h (6-bit) [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 99 12. i/o analog multiplexer this chapter explains the device-wide i/o analog multiplexer for the cy8ctmg20x and cy8ctst200 psoc devices and their associated registers. for a quick reference of all registers in address order, refer to the register reference chapter on page 187 . 12.1 architectural description the cy8ctmg20x and cy8ctst200 psoc devices con- tain an enhanced analog multiplexer (mux) capability. this function allows many i/o pins to connect to a common inter- nal analog global bus. you are able to connect any number of pins simultaneously, and dedicated support circuitry allows selected pins to be alternately charged high or connected to the bus. the ana- log global bus can be connected as a comparator input. figure 12-1 shows a block diagram of the i/o analog mux system. figure 12-1. i/o analog mux system for each pin, the mux capability exists in parallel with the normal gpio cell, shown in figure 12-2 . normally, the asso- ciated gpio pin is put into a high impedance state for these applications, although there are cases where the gpio cell is configured by the user to briefly drive pin initialization states as described ahead. pins are individually connected to the internal bus by setting the corresponding bits in the mux_crx registers. any num- ber of pins can be enabled at the same time. at reset, all of these mux connections are open (disconnected). figure 12-2. i/o pin configuration analog mux io pin device io pin analog mux bus io pin io pin gpio pin switch enable (mux_crx.n) analog mux bus discharge clock break- before-make circuitry [+] feedback
100 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i/o analog multiplexer 12.2 register definitions the following registers are only associated with the an alog bus mux in the cy8ctmg20x and cy8ctst200 psoc devices and are listed in address order. each register description has an associated register table showing the bit structure for that register. register bits that are grayed out throughout this do cument are reserved bits and are not detailed in the register descriptions that follow. always write reserved bits with a value of ?0?. 12.2.1 mux_crx registers the analog mux port bit enable registers (mux_cr0, mux_cr1, mux_cr2, mux_cr3, and mux_cr4) control the connection between the analog mux bus and the corre- sponding pin. bits 7 to 0: enable[7:0]. the bits in these registers enable connection of individual pins to the analog mux bus. each i/o port has a corresponding mux_crx register. setting a bit high connects the corresponding pin to the analog bus. for additional information, refer to the mux_crx register on page 271 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,d8h mux_cr0 enable[7:0] rw : 00 1,d9h mux_cr1 enable[7:0] rw : 00 1,dah mux_cr2 enable[7:0] rw : 00 1,dbh mux_cr3 enable[7:0] rw : 00 1,dfh mux_cr4 enable[3:0] rw : 0 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 101 13. comparators this chapter explains the co mparators for the cy8ctmg20x and cy8ctst200 psoc devices and their associated regis- ters. for a complete table of the comparator registers, refer to the truetouch register summary on page 84 . for a quick ref- erence of all registers in address order, refer to the register reference chapter on page 187 . 13.1 architectural description the cy8ctmg20x and cy8ctst200 psoc devices contain two comparators designed to support capacitive sensing or other general purpose uses. figure 13-1 shows a block diagram of the comparator system. figure 13-1. comparators block diagram lut cmp1 to: cap sense logic, cmp0 lut reg write amuxbus reserved p0[1] p0[3] vref reflo refhi reserved 2 comp1 enable, range (cmp_cr0) inn1[1:0] (cmp_mux) comparator analog system cmp1d (cmp_rdc) inp1[1:0] (cmp_mux) a b latch s r i/o read i/o read lut1[3:0] (cmp_lut) cmp1l (cmp_rdc) cmp1o to: pin outputs cds1 (cmp_cr1) crst1 (cmp_cr1) cpin1 (cmp_cr1) lut cmp0 to: cap sense logic, cmp1 lut reg write amuxbus reserved p0[1] p0[3] vref reflo refhi reserved 2 comp0 enable, range (cmp_cr0) inn0[1:0] (cmp_mux) cmp0d (cmp_rdc) inp0[1:0] (cmp_mux) a b latch s r i/o read i/o read lut0[3:0] (cmp_lut) cmp0l (cmp_rdc) cmp0o to: pin outputs cds0 (cmp_cr1) crst0 (cmp_cr1) cpin0 (cmp_cr1) cmp0 lut cmp1 lut cmp1 cint1 cmp0 cint0 to: analog interrupt lpf lpfilt[1:0] (cs_cr3) lpf_en[1] (cs_cr3) lpf_en[0] (cs_cr3) [+] feedback
102 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c comparators the comparator digital interface performs logic process- ing on one or more comparator signals, provides a latch- ing capability, and routes the result to other chip subsystems. the comparator signal is routed through a lookup table (lut) function. the other input to the lut is the neighboring comparator output. the lut implements 1 of 16 functions on the two inputs, as selected by the cmp_lut register. the lut output also feeds the set input upon a reset/set (rs) latch. the latch is cleared by writing a ?0? to the appropriate bit in the cmp_rdc regis- ter or by a rising edge from the other comparator lut. the primary output for each comparator is the lut output or its latched version. these are routed to the truetouch logic and to the interrupt controller. the comparator lut output state and latched state are directly read by the cpu through the cmp_rdc register. a selection of comparator state may also be driven to an output pin. when disabled, the comparators consume no power. two active modes provide a full rail-to-rail input range or a somewhat lower power option with limited input range. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 103 comparators 13.2 register definitions the following registers areassociated with the comparator s in the cy8ctmg20x and cy8ctst200 psoc devices and are listed in address order. for a complete table of the comparator registers, refer to the truetouch register summary on page 84 . each register description has an associated register tabl e showing the bit structure for that register. register bits that are grayed out throughout this document are reserved bits and are not detailed in the register descriptions that follow. always write reserved bits with a value of ?0?. 13.2.1 cmp_rdc register the comparator read/clear register (cmp_rdc) reads the state of the comparator data signal and the latched state of the comparator. bit 5: cmp1d. comparator 1 data state. this is a read only bit and returns the dynamically changing state of the comparator. bit 4: cmp0d. comparator 0 data state. this bit is a read-only bit and returns the dynamically changing state of the comparator. bit 1: cmp1l. comparator 1 latched state. this bit is set and held high whenever the comparator 1 lut goes high since the last time this register was read. refer to the crst1 bit in the cmp_cr1 register for information on how the latch is cleared. bit 0: cmp0l. comparator 0 latched state. this bit is set and held high whenever the comparator 0 lut goes high since the last time this register was read. refer to the crst0 bit in the cmp_cr1 register for information on how the latch is cleared. for additional information, refer to the cmp_rdc register on page 205 . 13.2.2 cmp_mux register the comparator multiplexer register (cmp_mux) con- tains control bits for input selection of comparators 0 and 1. bits 7 and 6: inp1[1:0]. these bits select the positive input. bits 5 and 4: inn1[1:0]. these bits select the negative input. bits 3 and 2: inp0[1:0]. these bits select the positive input data source for comparator 0. bits 1 and 0: inn0[1:0]. these bits select the negative input data source for comparator 0. for additional information, refer to the cmp_mux register on page 206 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,78h cmp_rdc cmp1d cmp0d cmp1l cmp0l # : 00 legend # access is bit specific. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,79h cmp_mux inp1[1:0] inn1[1:0] inp0[1:0] inn0[1:0] rw : 00 [+] feedback
104 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c comparators 13.2.3 cmp_cr0 register the comparator control register 0 (cmp_cr0) enables and configures the input range of the comparators. bit 4: cmp1en. this bit enables comparator 1. bit 0: cmp0en. this bit enables comparator 0. for additional information, refer to the cmp_cr0 register on page 207 . 13.2.4 cmp_cr1 register the comparator control register 1 (cmp_cr1) config- ures the comparator output options. bit 7: cint1. this bit connects the comparator 1 output to the analog output. bit 6: cpin1. this bit selects whether the comparator 1 lut output or the latched output is routed to a gpio pin. bit 5: crst1. this bit selects whether the comparator 1 latch is reset upon a register write or by a rising edge from the comparator 0 lut output. bit 4: cds1. this bit selects between the comparator 1 lut and the latched output for the main comparator out- put that drives to the capacitive sense and interrupt logic. bit 3: cint0. this bit connects the comparator 0 output to the analog output. bit 2: cpin0. this bit selects whether the comparator 0 lut output or the latched output is routed to a gpio pin. bit 1: crst0. this bit selects whether the comparator 0 latch is reset upon a register write or by a rising edge from the comparator 1 lut output. bit 0: cds0. this bit selects between the comparator 0 lut and the latched output for the main comparator out- put that drives to the capacitive sense and interrupt logic. for additional information, refer to the cmp_cr1 register on page 208 . 13.2.5 cmp_lut register the comparator lut control register (cmp_lut) selects the logic function. bits 7 to 4: lut1[3:0]. these bits control the selection of the lut 1 logic functions that may be selected for the com- parator channel 1. bits 3 to 0: lut0[3:0]. these bits control the selection of lut 0 logic functions that may be selected for the compara- tor channel 0. the selections are shown in the following table: for additional information, refer to the cmp_lut register on page 210 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,7ah cmp_cr0 cmp1en cmp0en rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,7bh cmp_cr1 cint1 cpin1 crst1 cds1 cint0 cpin0 crst0 cds0 rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,7ch cmp_lut lut1[3:0] lut0[3:0] rw : 00 lutx[3:0] 0h: 0000: false 1h: 0001: a .and. b 2h: 0010: a .and. b 3h: 0011: a 4h: 0100: a .and. b 5h: 0101: b 6h: 0110: a .xor. b 7h: 0111: a .or. b 8h: 1000: a .nor. b 9h: 1001: a .xnor. b ah: 1010: b bh: 1011: a .or. b ch: 1100: a dh: 1101: a .or. b eh: 1110: a. nand. b fh: 1111: true [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 105 section d: system resources the system resources section discusses the system resources that are available for the psoc devices and the registers associated with those res ources. this section encomp asses the following chapters: digital clocks on page 109 . i2c slave on page 117 . system resets on page 135 . por and lvd on page 143 . spi on page 145 . programmable timer on page 161 . full-speed usb on page 165 . top-level system re sources architecture the figure below displays the t op-level architecture of the psoc system resources. each component of the figure is dis- cussed at length in the chapters that follow. psoc system resources . system bus system resources i2c slave spi master/ slave por and lvd usb system resets three 16-bit programmable timers digital clocks [+] feedback
106 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section d: system resources system resources register summary the table below lists all the registers fo r the system resources, in address order, wi thin their system reso urce configuration . the bits that are grayed out are reserved bits. if you write these bits, always write them with a value of ?0?. summary table of the system resource registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access digital clock registers (page 112 ) 1,bdh usb_misc_c r usb_se_ en usb_on usb_clk_ on rw : 0 1,d1h out_p0 p0p7d p0p7en p0p4d p0p4en rw : 00 1,ddh out_p1 p16d p16en p14d p14en p12d p12en p10d p10en rw : 00 1,e0h osc_cr0 x32on disable buzz no buzz sleep[1:0] cpu speed[2:0] rw : 01 1,e2h osc_cr2 clk48men ext- clken imodis rw : 0 i2c slave registers (page 122 ) 0,c8h i2c_xcfg no bc int buffer mode hw addr en rw : 0 0,c9h i2c_xstat dir slave busy r: 0 0,cah i2c_addr slave address[6:0] rw : 00 0,cbh i2c_bp i2c base pointer[4:0] r : 00 0,cch i2c_cp i2c current pointer4:0] r : 00 0,cdh cpu_bp cpu base pointer4:0] rw: 00 0,ceh cpu_cp cpu current pointer4:0] r : 00 0,cfh i2c_buf data buffer[7:0] rw : 00 0,d6h i2c_cfg pselect stop ie clock rate[1:0] enable rw : 00 0,d7h i2c_scr bus error stop status ack address transmit lrb byte complete # : 00 0,d8h i2c_dr data[7:0] rw : 00 system reset registers (page 137 ) x,feh cpu_scr1 iress slimo[1:0] iramdis # : 0 x,ffh cpu_scr0 gies wdrs pors sleep stop # : xx por registers (page 143 ) 1,e3h vlt_cr porlev[1:0] lvdtben vm[2:0] rw : 00 1,e4h vlt_cmp nowrite por_ext lvd r : # spi registers (page 147 ) 0,29h spi_txr data[7:0] w : 00 0,2ah spi_rxr data[7:0] r : 00 0,2bh spi_cr lsb first overrun spi complete tx reg empty rx reg full clock phase clock polarity enable # : 00 1,29h spi_cfg clock sel [2:0] bypass ss_ ss_en_ int sel slave rw : 00 programmable timer registers (page 163 ) 0,b0h pt0_cfg clksel one shot start rw : 0 0,b1h pt0_data1 data[7:0] rw : 00 0,b2h pt0_data0 data[7:0] rw : 00 0,b3h pt1_cfg clksel one shot start rw : 0 0,b4h pt1_data1 data[7:0] rw : 00 0,b5h pt1_data0 data[7:0] rw : 00 0,b6h pt2_cfg clksel one shot start rw : 0 0,b7h pt2_data1 data[7:0] rw : 00 0,b8h pt2_data0 data[7:0] rw : 00 usb registers (page 171 ) 0,58h pmax_dr data byte[7:0] rw : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 107 section d: system resources 0,59h pmax_dr data byte[7:0] rw : 00 0,5ah pmax_dr data byte[7:0] rw : 00 0,5bh pmax_dr data byte[7:0] rw : 00 0,5ch pmax_dr data byte[7:0] rw : 00 0,5dh pmax_dr data byte[7:0] rw : 00 0,5eh pmax_dr data byte[7:0] rw : 00 0,5fh pmax_dr data byte[7:0] rw : 00 0,64h pmax_dr data byte[7:0] rw : 00 0,65h pmax_dr data byte[7:0] rw : 00 0,66h pmax_dr data byte[7:0] rw : 00 0,67h pmax_dr data byte[7:0] rw : 00 0,68h pmax_dr data byte[7:0] rw : 00 0,69h pmax_dr data byte[7:0] rw : 00 0,6ah pmax_dr data byte[7:0] rw : 00 0,6bh pmax_dr data byte[7:0] rw : 00 0,31h usb_sof0 frame number[7:0] r : 00 0,32h usb_sof1 frame number[10:8] r : 0 0,33h usb_cr0 usb enable device address[6:0] rw : 00 0,34h usbio_cr0 ten tse0 td rd # : 0 0,35h usbio_cr1 iomode drive mode dpi dmi ps2puen usb- puen dpo dmo rw : 00 0,41h epx_cnt1 data count[7:0] rw : 00 0,43h epx_cnt1 data count[7:0] rw : 00 0,45h epx_cnt1 data count[7:0] rw : 00 0,47h epx_cnt1 data count[7:0] rw : 00 0,49h epx_cnt1 data count[7:0] rw : 00 0,4bh epx_cnt1 data count[7:0] rw : 00 0,4dh epx_cnt1 data count[7:0] rw : 00 0,4fh epx_cnt1 data count[7:0] rw : 00 0,31h usb_sof0 frame number[7:0] r : 00 0,32h usb_sof1 frame number[10:8] r : 0 0,33h usb_cr0 usb enable device address[6:0] rw : 00 0,34h usbio_cr0 ten tse0 td rd # : 00 0,35h usbio_cr1 iomode drive mode dpi dmi pspuen usb- puen dpo dmo rw : 00 0,36h ep0_cr setup received in received out received ack?d transaction mode[3:0] rw : 00 0,37h ep0_cnt data toggle data valid byte count[3:0] # : 00 0,38h ep0_drx data byte[7:0] rw : 00 0,39h ep0_drx data byte[7:0] rw : 00 0,3ah ep0_drx data byte[7:0] rw : 00 0,3bh ep0_drx data byte[7:0] rw : 00 0,3ch ep0_drx data byte[7:0] rw : 00 0,3dh ep0_drx data byte[7:0] rw : 00 0,3eh ep0_drx data byte[7:0] rw : 00 0,3fh ep0_drx data byte[7:0] rw : 00 0,40h epx_cnt0 data toggle data valid count msb # : 0 0,42h epx_cnt0 data toggle data valid count msb # : 0 0,44h epx_cnt0 data toggle data valid count msb # : 0 summary table of the system resource registers (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access [+] feedback
108 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section d: system resources 0,46h epx_cnt0 data toggle data valid count msb # : 0 0,48h epx_cnt0 data toggle data valid count msb # : 0 0,4ah epx_cnt0 data toggle data valid count msb # : 0 0,4ch epx_cnt0 data toggle data valid count msb # : 0 0,4eh epx_cnt0 data toggle data valid count msb # : 0 1,30h usb_cr1 busactiv- ity enable- lock regenable rw : 0 1,34h pmax_wa write address[7:0] rw : 00 1,35h pmax_wa write address[7:0] rw : 00 1,36h pmax_wa write address[7:0] rw : 00 1,37h pmax_wa write address[7:0] rw : 00 1,38h pmax_wa write address[7:0] rw : 00 1,39h pmax_wa write address[7:0] rw : 00 1,3ah pmax_wa write address[7:0] rw : 00 1,3bh pmax_wa write address[7:0] rw : 00 1,44h pmax_wa write address[7:0] rw : 00 1,45h pmax_wa write address[7:0] rw : 00 1,46h pmax_wa write address[7:0] rw : 00 1,47h pmax_wa write address[7:0] rw : 00 1,48h pmax_wa write address[7:0] rw : 00 1,49h pmax_wa write address[7:0] rw : 00 1,4ah pmax_wa write address[7:0] rw : 00 1,4bh pmax_wa write address[7:0] rw : 00 1,3ch pmax_ra read address[7:0] rw : 00 1,3dh pmax_ra read address[7:0] rw : 00 1,3eh pmax_ra read address[7:0] rw : 00 1,3fh pmax_ra read address[7:0] rw : 00 1,40h pmax_ra read address[7:0] rw : 00 1,41h pmax_ra read address[7:0] rw : 00 1,42h pmax_ra read address[7:0] rw : 00 1,43h pmax_ra read address[7:0] rw : 00 1,4ch pmax_ra read address[7:0] rw : 00 1,4dh pmax_ra read address[7:0] rw : 00 1,4eh pmax_ra read address[7:0] rw : 00 1,4fh pmax_ra read address[7:0] rw : 00 1,50h pmax_ra read address[7:0] rw : 00 1,51h pmax_ra read address[7:0] rw : 00 1,52h pmax_ra read address[7:0] rw : 00 1,53h pmax_ra read address[7:0] rw : 00 1,54h epx_cr0 stall nak_int_en acked tx mode[3:0] # : 00 1,55h epx_cr0 stall nak_int_en acked tx mode[3:0] # : 00 1,56h epx_cr0 stall nak_int_en acked tx mode[3:0] # : 00 1,57h epx_cr0 stall nak_int_en acked tx mode[3:0] # : 00 1,58h epx_cr0 stall nak_int_en acked tx mode[3:0] # : 00 1,59h epx_cr0 stall nak_int_en acked tx mode[3:0] # : 00 1,5ah epx_cr0 stall nak_int_en acked tx mode[3:0] # : 00 1,5bh epx_cr0 stall nak_int_en acked tx mode[3:0] # : 00 summary table of the system resource registers (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 109 14. digital clocks this chapter discusses the digital clocks and their associated r egisters. it serves as an overview of the clocking options available in the psoc devices. for detailed information on specific oscillators, see the individual oscillator chapters in the sec- tion called psoc core on page 23 . for a complete table of the digital clock registers, refer to the system resources register summary on page 106 . for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 14.1 architectural description the psoc m8c core has a large number of clock sources that increase the flexibility of the psoc device, as listed in table 14-1 and illustrated in figure 14-1 . 14.1.1 internal main oscillator the internal main oscillator (imo) is the foundation upon which almost all other clock sources in the psoc device are based. the default mode of the imo creates a 12 mhz refer- ence clock that is used by many other circuits in the device. the psoc device has an option to replace the imo with an externally supplied clock that becomes the base for all of the clocks the imo normally serves . the internal base clock net is called sysclk and is driven by either the imo or an external clock (extclk). whether the external clock or the internal main oscillator is selected, all device functions are clocked from a derivative of sysclk or are resynchronized to sysclk. all external asynchronous signals and the internal low speed oscillator are resynchronized to sysclk fo r use in the digital blocks. the imo frequency can be adjusted to other frequencies besides 12 mhz. see the architectural description on page 63 , in the internal main oscillator chapter, for more information. the imo is discussed in detail in the chapter internal main oscillator (imo) on page 63 . table 14-1. system clocking signals and definitions signal definition sysclk either the direct out put of the internal main oscillator or the direct input of the extclk pin while in external clocking mode. cpuclk sysclk is divided down to one of eight possible frequencies to create cpuclk, which determines the speed of the m8c. see the osc_cr0 register in the register definitions sec- tion of this chapter. clk32k the internal low speed oscillators output. see the osc_cr0 register in the register definitions section of this chapter. clkim0 the internally generated clock from the imo. by default, this clock drives sysclk; however, an external clock may be used by enabling extclk mode. the imo can be set to var- ious frequencies; the default is 12 mhz. sleep one of four sleep intervals may be selected from 1.95 ms to 1 second. see the osc_cr0 register in the register defini- tions section of this chapter. [+] feedback
110 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c digital clocks 14.1.2 internal low speed oscillator the internal low speed oscillator (ilo) is available as a general clock, but is also the clock source for the sleep and watchdog timers. the ilo can be disabled in deep sleep mode, or in other sleep modes when the external crystal oscillator (eco) is enabled. the ilo is discussed in detail in the chapter internal low speed oscillator (ilo) on page 67 . figure 14-1. overview of psoc clock sources 14.1.3 external clock in addition to the imo clock source, an externally supplied clock may be selected as th e device master clock (see figure 14-1 ). pin p1[4] is the input pin for the external clock. if p1[4] is selected as the external clock source, the drive mode of the pin must be set to high z (not high z analog). an external clock with a frequency between 1 mhz and 24 mhz can be supplied. the reset state of the extclken bit is ?0?. with this setting the device always boots up under the control of the imo. the system cannot be started from a reset with the external clock. when the extclken bit is set, the external clock becomes the source for the internal clock tree, sysclk, which drives most psoc device clocking functions. all external and inter- nal signals, including the ilo or eco low frequency clock, are synchronized to this clock source. 14.1.3.1 switch operation switching between the imo and the external clock is done in firmware at any time and is transparent to the user. when a switch is made from the imo to the external clock, turn off the imo to save power. you do this by setting the imodis bit immediately after the instruction that sets the extclken bit. when switching back from an external clock to the imo, clear the imodis bit and implement a firmware delay. this gives the imo sufficient startup time before the extclken bit is cleared. switch timing depends upon whether the cpu clock divider is set for divide by 1, or divide by 2 or greater. in the case where the cpu clock divider is set for divide by 2 or greater, as shown in figure 14-2 , the setting of the extclken bit occurs shortly after the rising edge of sysclk. the sysclk output is then disabled after the next falling edge of sysclk, but before the next rising edge. this ensures a glitch free transition and provides a full cycle of setup time from sysclk to output disable. after the current clock selection is disabled, the enable of the newly selected clock is double synchronized to that clock. after synchronization, on the subsequent negative edge, sysclk is enabled to output the newly selected clock. in the 12 mhz case, as shown in figure 14-3 , the assertion of iow_ and thus the setting of the extclken bit occurs on the falling edge of sysclk. since sysclk is already low, the output is immediately disabled. therefore, the setup time from sysclk to disable is one-half sysclk. sysclk cpuclk sleep internal main oscillator (imo) imo trim register clk32k extclk p1[4] (extclk input) imo_tr[7:0] osc_cr2[2] clock divider osc_cr0[2:0] sleep clock divider osc_cr0[4:3] 2 6 2 9 2 12 2 15 slow imo option cpu_scr1[4:3] 1 2 4 8 16 32 128 256 ilo trim register internal low speed oscillator (ilo) ilo_tr[7:0] [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 111 digital clocks figure 14-2. switch from imo to the external clock with a cpu clock divider of two or greater figure 14-3. switch from imo to external clock with the cpu running with a cpu clock divider of one cpuclk imo extenal clock sysclk iow_ extclk bit imo is disabled. external clock is enabled. cpuclk imo external clock sysclk iow extclk imo is disabled. external clock is enabled. [+] feedback
112 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c digital clocks 14.2 register definitions the following registers are associ ated with the digital clocks and are listed in address order. each register description has a n associated register table showing the bit structure for that register. the bits in the tables that are grayed out throughout th is manual are reserved bits and are not detailed in the register de scriptions that follow. always write reserved bits with a value of ?0?. for a complete table of digital clock registers, refer to the ?system resources register summary? on page 106 . 14.2.1 usb_misc_cr register the usb miscellaneous control register controls the clocks to the usb block, to make the imo work with better accu- racy for the usb part and to disable the single ended input of the usbio in the case of a non-usb part. bit 2: usb_se_en. the single ended outputs of usbio is enabled or disabled based upon this bit setting. set this bit to '1' when using this part as a usb part for usb transac- tions to occur. set this bit to '0' to disable single ended out- puts of usbio. the dpo, dmo are held at logic high state and rse0 is held at a low state. note bit [1:0] of the usbio_cr1 register is also affected depending on this register setting. when this bit is '0' (default), regardless of the dp and dm state, the dpo and dmo bits of usbio_cr1 are '11b'. bit 1: usb_on. this bit is used by the imo dac block to either work with better dnl consuming higher power, or with sacrificed dnl consuming lower power. set this bit to '1' when the part is used as a usb part. a '0' runs the imo with sacrificed dnl by consuming less power. a '1' runs the imo with better dnl by consuming more power. bit 0: usb_clk_on. this bit either enables or disables the clocks to the usb block. it is used to save power in cases when the device need not respond to usb traffic. set this bit to '1' when the device is used as a usb part. when this bit is a ?0?, all clocks to the usb block are driven. the device does not respond to usb traffic and none of the usb registers, except imo_tr, imo_tr1 and usbio_cr1, listed in the register definitions on page 171 are writable. when this bit is a ?1?, clocks are not blocked to the usb block. the device responds to usb traffic depending on the other register settings mentioned under register definitions in the full-speed usb chapter on page 165 . for additional information, refer to the usb_misc_cr reg- ister on page 267 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,bdh usb_misc_cr usb_se_en usb_on usb_clk_on rw : 0 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 113 digital clocks 14.2.2 out_p0 register this register enables specific internal signals to be output to port 0 pins. the gpio drive modes must be specified to support the desired output mode (registers prt0dm1 and prt0dm0). if a pin is enabled for output by a bit in this reg- ister, the corresponding signal has priority over any other internal function that may be configured to output to that pin. bit 7: p0p7d. ?0? selects main system clock (sysclk). ?1? selects truetouch signal depending on prs_cr and cs_cr0 register settings. bit 6: p0p7en. this bit enables pin p0[7] for output of the signal selected by p0p7d. ?0 ?is no internal signal output to p0[7]. ?1? outputs the signal selected by p0p7d onto p0[7]. bit 5: p0p4d. ?0? selects timer outp ut (timerout). ?1? selects clk32. note : during sleep mode these outputs will not be passed through to p0[4]. bit 4: p0p4en. this bit enables pin p0[4] for output of the signal selected by p0p4d. ?0? is no internal signal output to p0[4]. ?1? outputs the signal selected by p0p4d onto p0[4]. 14.2.3 out_p1 register the output override to port 1 register (out_p1) enables specific internal signals to output to port 1 pins. if any other function, such as i2c, is enabled for output on these pins, that function has higher priority than the out_p1 signals. bit 7: p16d. bit selects the data output to p1[6] when p16en is high. in cy8ctmg20x and cy8ctst200 timer output and clk32 are available on p0[4] as well, but out- puts on p0[4] will not be passed through during sleep modes. please refer to the out_p0 register for more details. 0 - select timer output (timerout) 1 - select clk32 bit 6: p16en. this bit enables pin p1[6] for signal output selected by the p16d bit. 0 - no internal signal output to p1[6] 1 - output the signal selected by p16d to p1[6] bit 5: p14d. this bit selects the data output to p1[4] when p14en is high and 14db is low. bit 4: p14en. this bit enables pin p1[4] for output of the signal selected by the p14d bit. bit 3: p12d. this bit selects data output to p1[2] when p12en is high. truetouch signals are available on p0[7] as well. please refer out_p0 register for more details. bit 2: p12en. this bit enables pin p1[2] for output of the signal selected by the p12d bit. bit 1: p10d. this bit selects data output to p1[0] when p10en is high. bit 0: p10en. bit enables pin p1[0] for output of the signal selected by the p10d bit. 0 - no internal signal output to p1[0] 1 - output the signal selected by p10d to p1[0] for additional information, refer to the out_p1 register on page 273 . 14.2.4 osc_cr0 register the oscillator control regi ster 0 (osc_cr0) configures various features of internal clock sources and clock nets. bit 7: x32on. this bit enables the 32 khz external crystal oscillator (eco) when set high. see the application over- address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,d1h out_p0 p0p7d p0p7en p0p4d p0p4en rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,ddh out_p1 p16d p16en p14d p14en p12d p12en p10d p10en rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,e0h osc_cr0 x32on disable buzz no buzz sleep[1:0] cpu speed[2:0] rw : 01 [+] feedback
114 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c digital clocks view on page 70 for the proper sequence to enable the eco. bit 6: disable buzz. setting this bit high causes the band- gap and por/lvd systems to re main powered off continu- ously during sleep. in this case, there is no periodic ?buzz? (brief wakeup) of these functions during sleep. this bit has no effect when the no buzz bit is set high. bit 5: no buzz. normally, when the sleep bit is set in the cpu_scr register, all psocdevice systems are powered down, including the bandgap reference. however, to facili- tate the detection of por and lvd events at a rate higher than the sleep interval, the bandgap circuit is powered up periodically (for about 60 s) at the sleep system duty cycle, which is independent of the sleep interval and typi- cally higher. when the no buzz bit is set, the sleep system duty cycle value is overwritten and the bandgap circuit is forced to be on during sleep. this results in faster response to an lvd or por event (continuous detection as opposed to periodic), at the expense of higher average sleep current. bits 4 and 3: sleep[1:0]. the available sleep interval selections are shown in the table below. sleep intervals are approximate based upon the accuracy of the internal low speed oscillator. bits 2 to 0: cpu speed[2:0]. the m8c operates over a range of cpu clock speeds, allowing you to tailor the m8c?s performance and power requirements to the application. the reset value for the cpu speed bits is 010b. therefore, the default cpu speed is one-half of the clock source. the internal main oscillator is the default clock source for the cpu speed circuit; therefore, the default cpu speed is 6.0 mhz. see external clock on page 110 for more information on the supported fr equencies for externally supplied clocks. the cpu frequency is changed with a write to the osc_cr0 register. there are eight frequencies generated from a power-of-two divide circuit that is selected by a 3-bit code. at any given time, the cp u 8-to-1 clock mux is select- ing one of the available frequencies, which is resynchro- nized to the 24 mhz master clock at the output. the imo frequency is also selectable, as discussed in the imo chap- ter in the architectural description on page 63 . this offers an option to lower both syst em and cpu clock speed to save power. the selections are shown in the table below (reset state is 001b). an automatic protection mechanism is available for systems that need to run at peak cpu clock speed but cannot guar- antee a high enough supply voltage for that clock speed. see the lvdtben bit in the vlt_cmp register on page 144 for more information. note during usb operation, the cpu speed can be set to any setting. be aware that usb throughput decreases with a decrease in cpu speed. for maximum throughput, the cpu clock should be made equal to the system clock. the sys- tem clock must be 24 mhz for usb operation. for additional information, refer to the osc_cr0 register on page 276 . sleep interval osc_cr[4:3] sleep timer clocks sleep period (nominal) watchdog period (nominal) 00b (default) 64 1.95 ms 6 ms 01b 512 15.6 ms 47 ms 10b 4096 125 ms 375 ms 11b 32,768 1 sec 3 sec bits 6 mhz internal main oscillator 12 mhz internal main oscillator 24 mhz internal main oscillator external clock 000b 750 khz 1.5 mhz 3 mhz extclk/ 8 001b 1.5 mhz 3.0 mhz 6 mhz extclk/ 4 010b 3 mhz 6.0 mhz 12 mhz extclk/ 2 011b 6 mhz 12.0 mhz 24 mhz extclk/ 1 100b 375 khz 750 hz 1.5 mhz extclk/ 16 101b 187.5 khz 375 khz 750 khz extclk/ 32 110b 46.8 khz 93.7 khz 187.5 khz extclk/ 128 111b 23.4 khz 46.8 khz 93.7 khz extclk/ 256 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 115 digital clocks 14.2.5 osc_cr2 register the oscillator control register 2 (osc_cr2) configures various features of internal clock sources and clock nets. bit 4: clk48men. this is the 48 mhz clock enable bit. '0' disables the bit and '1' enables the bit. this register set- ting applies only when the device is not in ocd mode. when in ocd mode, the 48 mhz clock is always active. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,e2h osc_cr2 clk48men extclken imodis rw : 00 [+] feedback
116 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c digital clocks bit 2: extclken. when the extclken bit is set, the external clock becomes the source for the internal clock tree, sysclk, which drives most device clocking functions. all external and internal signals, including the low speed oscillator, are synchronized to this clock source. the exter- nal clock input operates from the clock supplied at p1[4] or p1[1] based on the tsync bit in cpu_scr1. when using this input, the pin drive mode must be set to high z (not high z analog), such as drive mode 11b with the prt1dr bit 4 set high. bit 1: imodis. when set, the internal main oscillator (imo) is disabled. for additional information, refer to the osc_cr2 register on page 278 . [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 117 15. i 2 c slave this chapter explains the i 2 c slave block and its associated registers. the i 2 c communications block is a serial processor designed to implement a complete i 2 c slave. for a complete table of the i 2 c registers, refer to the summary table of the sys- tem resource registers on page 106 . for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 15.1 architectural description the i 2 c slave enhanced communications block is a serial-to-paralle l processor, designed to interface the psoc device to a two-wire i 2 c serial communications bus. to eliminate the need for excessive cpu intervention and overhead, the block pro- vides i 2 c-specific support for status detection and generation of framing bits. by default, the i 2 c slave enhanced module is firmware compatible with the previous generation of i 2 c slave functionality. however, this module provides new features that are configurable to implement significant flexibility for both internal and external interfacing. figure 15-1. i 2 c block diagram basic i 2 c features include: slave, transmitter, and receiver operation byte processing for low cpu overhead interrupt or pollin g cpu interface support for clock rates of up to 400 khz 7- or 10-bit addressing (through firmware support) smbus operation (through firmware support) enhanced features of the i 2 c slave enhanced module include: support for 7-bit hardware address compare flexible data buffering schemes a "no bus stalling" operating mode a low power bus monitoring mode i2c core i2c basic configuration i2c_cfg i2c_scr i2c_dr plus features hw addr cmp buffer module cpu port buffer ctl 32 byte ram i2c plus slave i2c_addr sda_out scl_in sysclk i2c_en to/from gpio pins standby scl_out sda_in i2c_xstat i2c_xcfg i2c_buf i2c_bp i2c_cp mcu_cp mcu_bp system bus [+] feedback
118 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c slave the i 2 c block controls the data (sda) and the clock (scl) to the external i 2 c interface through direct connections to two dedicated gpio pins. when i 2 c is enabled, these gpio pins are not available for general purpose use. the psoc cpu firmware interacts with the block through i/o register reads and writes, and firmware synchronization is imple- mented through polling and/or interrupts. in the default operating mode, which is firmware compatible with previous versions of i 2 c slave modules, the i 2 c bus is stalled upon every received address or byte, and the cpu is required to read the data or supply data as required before the i 2 c bus continues. however, this i 2 c slave enhanced module provides new data buffering capability as an enhanced feature. in the ezi2c buffering mode, the i 2 c slave interface appears as a 32-byte ram buffer to the external i 2 c master. using a simple predefined protocol, the master controls the read and write pointers into the ram. when this method is enabled, the slave never stalls the bus. in this protocol, the data available in the ram (this is man- aged by the cpu) is valid. 15.1.1 basic i 2 c data transfer figure 15-2 shows the basic form of data transfers on the i 2 c bus with a 7-bit address format. for a more detailed description, see the philips semiconductors (now nxp semiconductors) i 2 c-bus specification, version 2.1. a start condition (generated by the master) is followed by a data byte, consisting of a 7-bit slave address (there is also a 10-bit address mode) and a read/write (rw) bit. the rw bit sets the direction of data transfer. the addressed slave is required to acknowledge (ack) the bus by pulling the data line low during the ninth bit time. if the ack is received, the transfer proceeds and the master transmits or receives an indeterminate number of bytes, depending upon the rw direction. if, for any reason, the slave does not respond with an ack, a stop condition is generated by the master to ter- minate the transfer or a rest art condition is generated for a retry attempt. figure 15-2. basic i 2 c data transfer with 7-bit address format 15.2 application overview there are two modes of slave operation, which are differen- tiated by how the i 2 c block synchronize s cpu interaction, how and when stalling of the i 2 c bus is done, and data buff- ered. 15.2.1 slave operation when slave mode is enabled, it is continually listening on the bus for a start condition. when detected, the transmitted address/rw byte is received and read from the i 2 c block by firmware. at the point where eight bits of the address/rw byte are received, a byte complete interrupt is generated. on the following low of the clock, the bus is stalled by hold- ing the scl line low until the psoc device has had a chance to read the address byte and compare it to its own address. it issues an ack or nack command based upon that com- parison. if there is an address match, the rw bit determines how the psoc device sequences the data transfer in slave mode, as shown in the two branches of figure 15-3 . i 2 c handshaking methodology (slave holds the scl line low to ?stall? the bus) is used, as necessary, to give the psoc device time to respond to the events and conditions on the bus. figure 15-3 is a graphical representation of a typical data transfer from the slave perspective. 178 9 178 9 start 7-bit address r/w ack 8-bit data ack/nack stop [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 119 i2c slave figure 15-3. slave operation 15.2.2 ezi2c mode when ezi2c mode is configured with the buffer mode bit of the i2c_xcfg register, both the master and slave must use a predefined communication protocol. in this protocol, the i 2 c slave operates as a ram buffer interface, in which the external master controls the read and write addresses to the 32-byte ram buffer. the external master reads and writes to the ram buffer are independent of the cpu reads and writes to the ram buffer, so conceptually, it appears as a dual port ram buffer. higher level protocols, such as polling or semaphore methods, are used to ensure data synchroni- zation and integrity. conceptually, data is always available in this mode so the bus never stalls except in i 2 c sleep mode. the ram buffer interfaces contain separate address point- ers, i2c_bp and i2c_cp, that are set with the first data byte of a write operation. when the external master writes one or more bytes, the first data byte is always the base address pointer value. this value gets written to both the base address pointer, i2c_bp, and the current address pointer, i2c_cp. the byte after the base address pointer is written into the location pointed to by the current address pointer value contained in i2c_cp. the third byte (second data byte) is written to the current address pointer value, i2c_cp, plus one and so on. this current address pointer, i2c_cp, increments for each byte read or written, but is reset to the base address pointer value at the beginning of each new write or read operation (following a start command). for example, if the base address pointer, i2c_bp, is set to 4, a read operation begins to read data at location 4 and continues sequentially until the host completes the read operation. so, if the base address pointer is set to 4, each read operation resets the data pointer to 4 and reads sequentially from that location. this is true whether single or multiple read operations are performed. the base address pointer is not changed until a new write operation initiates. if the i 2 c master attempts to write data past the ram address boundary, 32 bytes, the data is discarded and does not affect any ram inside or outside the designated ram area. you cannot read data outside the allowed range. any read requests by the master outside the allowed range result in the return of invalid data. if the ram address is sent 178 178 9 star t 7-bit address r/w ack 8-bit data ack/nack stop shifter m8c reads the received byte from the i2c_dr register and checks for ?own address? and r/w. 178 8-bit data stop shifter m8c writes the byte to transmit to the i2c_dr register. 9 shifter re ad (t x ) w r i t e ( r x ) m8c writes (ack) to i2c_scr register. slave transmitter/reciever ack/nack m8c issues ack/nack command with a write to the i2c_scr register. master may transmit another byte or stop. m8c reads the received byte from the i2c_dr register. ack = master wants to read another byte. nack = master says end-of-data. nack = slave says no more. ack = ok to receive more. a byte interrupt is generated. the scl line is held low. an interrupt is generated on byte complete. the scl line is held low. an interrupt is generated on a complete byte + ack/nack. the scl line is held low. ack m8c writes (ack | transmit) to i2c_scr register. 9 m8c writes a new byte to the i2c_dr register and then writes a transmit command to i2c_scr to release the bus. [+] feedback
120 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c slave by the external master through a write command and if the pointer value exceeds 1fh, a nack is sent. the following diagram illustrates the bus communication for a data write, a data pointer write, and a data read operation. remember that a data write operation always rewrites the data pointer. figure 15-4. two-wire interface bus communication a a a a a a a 6 5 4 3 2 1 0 r w s a a d d d d d d d d 7 6 5 4 3 2 1 0 a d d d d d d d d 7 6 5 4 3 2 1 0 a d d d d d d d d 7 6 5 4 3 2 1 0 a p a a a a a a a 6 5 4 3 2 1 0 s a a p a a a a a a a 6 5 4 3 2 1 0 r w s a a r r r r r r r r 7 6 5 4 3 2 1 0 a d d d d d d d d 7 6 5 4 3 2 1 0 a d d d d d d d d 7 6 5 4 3 2 1 0 a p d d d d d d d d 7 6 5 4 3 2 1 0 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r 7 6 5 4 3 2 1 0 r w slave addr data address(n) data(n) data(n+1) data(n+x) data address(n) data(n) data(n+1) data(n+x) data(n+2) master slave legend slave addr slave addr ack write write write stop no ack ack stop ack ack ack ack ack ack ack ack ack stop start star t star t write x bytes to i2c slave set slave data pointer read x bytes to i2c slave [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 121 i2c slave the following diagram illustrates an example of how the address pointers are configured in ezi2c mode. in this example, the external master sent a start, slave address, and a data byte of 2 to initialize both the base address pointer (i2c_bp register) and the current address pointer (i2c_cp register). then, 4 bytes were written, or a start or restart was sent with the device address, and 4 bytes were read. on the cpu side, a 2 was writ ten to the cpu base address register (cpu_bp register), and 6 subsequent bytes were read from or writt en to the i2c_buff register by the cpu. figure 15-5. address pointer in ezi2c mode 0 1 2 3 4 5 6 7 8 9 32-byte ram 8 2 2 6 buffer module i2c base pointer (i2c_bp) i2c current pointer (i2c_cp) cpu base pointer (cpu_bp) cpu current pointer (cpu_cp) transmit data bytes from cpu (cpu write to i2c_buff) receive data bytes to cpu (cpu read from i2c_buff) transmit data bytes to i2c interface receive data bytes from i2c interface [+] feedback
122 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c slave 15.3 register definitions the registers shown here are associated with i 2 c slave and are listed in address order. each register description has an associated register table showing the bit structure for that regist er. the grayed out bits in the tables are reserved bits and are not detailed in the register descriptions that follow. always write reserved bits with a value of ?0?. for a complete table of i 2 c registers, refer to the ?summary table of the system resource registers? on page 106 . 15.3.1 i2c_xcfg register the i 2 c extended control register (i2c_xcfg) configures enhanced features. when all bits are left in the default reset state of ?0?, the block operates in compatibility mode. bits 0 through 3 (except bit 2) are rw. the enable bit (bit 0) of the i2c_cfg (0,d6h) register should be set to 1'b1 for the i 2 c enhanced features to work. bit 3: no bc int. in compatibility mode, every received or transmitted byte generates a byte complete interrupt. this is also true in buffered mode regardless of whether the bus is stalled or not. note when this bit is set to a ?1?, a bc interrupt is not enabled for any data byte that is automatically ack?ed (i.e., does not require the bus to stall). a bc interrupt is always generated on any stall so the cpu takes the appropriate action. when the bit is set, it is possible to implement packet transfers without cpu intervention by enabling an interrupt upon the stop detect. bit 1: buffer mode. this bit determines the operation mode of the enhanced buffer module. the following table describes the available modes. bit 0: hw addr en. when this bit is set to a ?1?, hardware address compare is enabled. upon a compare, the address is automatically ack?ed, and upon a mismatch, the address is automatically nack?ed and the hardware reverts to an idle state waiting for the next start detection. you must con- figure the compare address in the i2c_addr register. when this bit is a ?0?, bit 3 of the i2c_scr register is set and the bus stalls, and the received address is available in the i2c_dr register to enable the cpu to do a firmware address compare. the functionality of this bit is independent of the data buffering mode. for additional information, refer to the i2c_xcfg register on page 226 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,c8h i2c_xcfg no bc int buffer mode hw addr en rw : 0 hw addr en buffer mode no bc lnt byte complete interrupt clock (scl) stalling on on on no interrupt. no stalling. off interrupt generated upon every byte. a a. non-address bc interrupts are only posted if the bc bit is cleared in i2c_scr. putting the m8c to sleep without clearing the bc bit in i2c_scr will mask i 2 c interrupts. this will stall the i 2 c bus. on off on interrupt generated upon every byte. b b. enabling no bc int has no affect when hw addr en is enabled and buff- er mode is disabled, even at address byte. the reason is that the receive/ transmit bit must be set by the cpu. in the case of transmit operation, the byte to transmit must be loaded to the i2c_data register. scl stalls at each byte. off interrupt generated upon every byte. off on on generated only at address byte. c c. enabling no bc int has no affect onl y at address byte in this configura- tion. the reason is that the cpu must write to the ack bit in the i2c_scr register to ack/nack the address byte. scl stalls only at address byte. off interrupt generated upon every byte. a off off on interrupt generated upon every byte. d d. enabling no bc int has no affect in compatibility mode. scl stalls at every byte. off interrupt generated upon every byte. buffer mode name description 0compatible there is no buffering in the default compatibility mode. the i 2 c bus is stalled upon every received or transmitted byte, including address bytes. the cpu is required to process the interrupt and write or read the data and status as required to continue the operation. 1ezi2c the i 2 c slave appears as a 32-byte ram inter- face to an external master. a specific protocol must be followed, in which the master controls the ram pointer for both read and write operations. the i 2 c bus is never stalled. receive acks are auto- matically generated. the cpu is responsible for putting valid data into the ram for external reads, and for reading received data. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 123 i2c slave 15.3.2 i2c_xstat register the i 2 c extended status register (i2c_xstat) reads enhanced feature status. all bits are read only. when the bits of i2c_xcfg are left in their reset state, the block is in compatibility mode, and this register is not in use. bit 1: dir. this bit indicates the direction of the current transfer. a ?1? indicates a master read, and a ?0? indicates a master write. it is only valid when the slave busy bit (bit 0) is set to ?1?. bits 0: slave busy. this bit is set upon a hardware address compare and is reset upon the following stop sig- nal. poll this bit to determine when the slave is busy and the buffer module is being accessed. for additional information, refer to the i2c_xstat register on page 227 . 15.3.3 i2c_addr register the i 2 c slave address register (i2c_addr) holds the slave?s 7-bit address. all bits are rw. note when hardware address compare mode is not enabled in the i2c_xcfg register, this register is not in use. bits 6 to 0: slave address[6:0] . these 7 bits hold the slave?s own device address. for additional information, refer to the i2c_addr register on page 228 . 15.3.4 i2c_bp register the i 2 c base address pointer register (i2c_bp) contains the base address value of the ram data buffer. note when in compatibility mode, this register is not in use. bits 4 to 0: i2c base pointer[4:0]. in the ezi2c protocol, the first data byte after the slave address transaction in write mode is the base address for subsequent reads and writes and it is transferred directly into this register. if the desired transaction is a master write to the slave, subsequent bytes are written to the ram buffer starting with this address and auto incremented (see i2c_cp register ). in case of a read, a start or restart must be issued and the read location starts with this address and again subsequent read addresses are auto incremented as pointed to by the i2c_cp register value. the value of this register is modified only at the beginning of every i 2 c write transaction. the i 2 c master must always supply a va lue for this register in the first byte of data after the slave?s address in a given write transaction. if performing reads, the master need not set the value of this register. the current value of this register is also used directly for reads. for additional information, refer to the i2c_bp register on page 229 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,c9h i2c_xstat dir slave busy r : 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,cah i2c_addr slave address[6:0] rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,cbh i2c_bp i2c base pointer[4:0] r : 00 [+] feedback
124 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c slave 15.3.5 i2c_cp register the i 2 c current address pointer register (i2c_cp) con- tains the current address value of the ram data buffer. note when in compatibility mode, th is register is not in use. bits 4 to 0: i2c current pointer[4:0]. this register gets set at the same time and with the same value as the i2c_bp register . after each completed data byte of the current i 2 c transaction, the value of this register is incremented by one. the value rolls over to 0x00 when the master writes the 32nd byte. the value of this register always determines the location that read or write data comes from or is written to. this reg- ister is set to the value contained in the i2c_bp register on every start condition detected in the bus. for additional information, refer to the i2c_cp register on page 230 . 15.3.6 cpu_bp register the cpu base address pointer register (cpu_bp) con- tains the base address value of the ram data buffer. note when in compatibility mode, th is register is not in use. bits 4 to 0: cpu base pointer[4:0]. this register value is completely controlled by i/o writes by the cpu. firmware routines must set this register. as with the i2c_bp, the value of this register sets the starting address for the data location being written or read. when this register is written, the cur- rent address pointer, cpu_cp, is also updated with the same value. the first read or write from/to the i2c_ buf register start at this address. the location of the data in subsequent read or writes is determined by the cpu_cp register value, which auto increments after each read or write. firmware makes certain that the slave device always has valid data or the data is read before overwritten. for additional information, refer to the cpu_bp register on page 231 . 15.3.7 cpu_cp register the cpu current address pointer register (cpu_cp) con- tains the current address value of the ram data buffer. note when in compatibility mode, th is register is not in use. bits 4 to 0: cpu current pointer[4:0]. this register is set at the same time and with the same value as the cpu_bp register . whenever the i2c_buf register is written or read, the cpu_cp increments automatically. for additional information, refer to the cpu_cp register on page 232 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,cch i2c_cp i2c current pointer[4:0] r : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,cdh cpu_bp cpu base pointer[4:0] rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,ceh cpu_cp cpu current pointer[4:0] r : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 125 i2c slave 15.3.8 i2c_buf register the i 2 c data buffer register (i2c_buf) is the cpu read/ write interface to the data buffer. whenever this register is read, the data at the location pointed to by the cpu current pointer (cpu_cp) is returned. similarly, whenever this reg- ister is written, the data is transferred to the buffer and writ- ten at the location pointed to by the cpu current pointer (cpu_cp). whenever this register is read, without initializ- ing the ram contents either through the i 2 c or cpu inter- face, no valid va lue is returned. the m8c accesses the data buffer through this register interface (i2c_buf). since the m8c issues an i/o read sig- nal before an i/o write for some opcodes, the pointers (cpu_cp) to the data buffer increment unnecessarily because of an extra i/o read before an i/o write. hence, all the i/o reads that occur in first phase are ignored. the i/ o reads that occur only in exec phase are taken as actual i/o reads for this register. so, only the following basic m8c register access instruc- tions may be used for accessing this register: mov a, reg[expr] mov a, reg[x+expr] mov [expr], [expr] mov reg[expr], a mov reg[x+expr], a mov reg[expr], expr mov reg[x+expr], expr note when in compatibility mode, th is register is not in use. bits 7 to 0: data buffer[7:0]. the i 2 c data buffer regis- ter (i2c_buf) is the cpu read/write interface to the data buffer. whenever this register is read, the data at the loca- tion pointed to by the cpu current pointer (cpu_cp) is returned. similarly, whenever this register is written, the data is transferred to the buffer and written at the location pointed to by the cpu current pointer (cpu_cp). whenever this register is read, without initializing the ram contents either through the i 2 c or cpu interface, no valid value is returned. for additional information, refer to the i2c_buf register on page 233 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,cfh i2c_buf data buffer[7:0] rw : 00 [+] feedback
126 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c slave 15.3.9 i2c_cfg register the i 2 c configuration register (i2c_cfg) is used to set the basic operating modes, baud rate, and selection of inter- rupts. the bits in this register control baud rate selection and optional interrupts. the values are typically set once for a given configuration. the bits in this register are all rw. bit 6: pselect. pin select. with the default value of zero, the i 2 c pins are p1[7] for clock and p1[5] for data. when this bit is set, the pins for i 2 c switch to p1[1] for clock and p1[0] for data. you cannot change this bit while the enable bit is set. however, the pselect bit may be set at the same time as the enable bits. the two sets of pins used on i 2 c are not equivalent. the default set, p1[7] and p1[5], are the pre- ferred set. the alternate set, p1[1] and p1[0], are provided so that i 2 c may be used with 8-pin psoc devices. if in-system serial programming (issp) is used and the alternate i 2 c pin set is also used, you must consider the interaction between the psoc test controller and the i 2 c bus. the interface requiremen ts for issp must be reviewed to ensure that they are not violated. even if issp is not used, pins p1[1] and p1[0] respond dif- ferently than other i/o pins to a por or xres event. after an xres event, both pins are pulled down to ground by going into the resistive zero drive mode before reaching the high z drive mode. after a por event, p1[0] drives out a one, then goes to the resistive zero state for some time, and finally reaches the high z drive mode state. after por, p1[1] goes into a resistive zero state for a while before going to the high z drive mode. bit 4: stop ie. stop interrupt enable. when this bit is set, a slave can interrupt upon stop detection. the status bit asso- ciated with this interrupt is the stop status bit in the i2c_scr register . when the stop status bit transitions from ?0? to ?1?, the interrupt is generated. it is important to note that the stop status bit is not automatically cleared. therefore, if it is already set, no new interrupts are gener- ated until it is cleared by firmware. bits 3 and 2: clock rate[1:0]. these bits offer a selection of three sampling and bit rates. all block clocking is based on the sysclk input, which is nominally 12 mhz or 6 mhz or 24 mhz for cy8ctmg20x and cy8ctst200 (unless the psoc device is in external clocking mode). the sampling rate and the baud rate are determined as follows: sample rate = sysclk/prescale factor baud rate = 1/(sample rate x samples per bit) when clocking the input with a frequency other than 6/12 mhz (for example, clocking the device with an external clock), the baud rates and sampling rates scale accordingly. whether the block works in a standard mode or fast mode system depends upon the sample rate. the sample rate must be sufficient to resolve bus events, such as start and stop conditions. see the philips semicon- ductors (now nxp semiconductors) i 2 c-bus specification, version 2.1, for minimum start and stop hold times. bit 0: enable. when the slave is enabled, the block gener- ates an interrupt upon any start condition and an address byte that it receives indicating the beginning of an i 2 c trans- fer. when operating as a slave, the block is clocked from an external master. therefore, the block works at any fre- quency up to the maximum defined by the currently selected clock rate. the internal clock is only used in slave mode, to ensure that there is adequate setup time from data output to the next clock upon the release of a slave stall. when the enable bit is ?0?, the block is held in reset and all status is cleared. cpu access to the hw buffer (ezi2c mode) is blocked when the bit is '0'. block enable is synchronized to the sysclk clock input ( see ?timing diagrams? on page 130 ). if the block is enabled when there is an i 2 c transaction already on the i 2 c bus, an erroneous start is detected if scl is high and sda is low. (sda in this case is low because of a data/ack bit.) thus, to avoid this erroneous start detection, enable the block only when the bus is idle (scl and sda are high when idle) or only when both scl and sda are low. the other option is to change the drive modes of the i 2 c pins to be other than open drain mode and then enable the address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,d6h i2c_cfg pselect stop ie clock rate[1:0] enable rw : 00 table 15-1. i2c_cfg configuration register bit access description mode 6 rw i2c pin select 0 = p1[7], p1[5] 1 = p1[1], p1[0] slave 4 rw stop ie stop interrupt enable. 0 = disabled. 1 = enabled. an interrupt is generated upon the detection of a stop condition. slave 3:2 rw clock rate 00 = 100k standard mode 01 = 400k fast mode 10 = 50k standard mode 11 = reserved slave [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 127 i2c slave i 2 c block. after enabling the i 2 c block, wait for 3 i 2 c sample clocks, then configure th e drive modes of the i 2 c pins to be in open drain mode. for additional information, refer to the i2c_cfg register on page 239 . table 15-2. enable operation in i2c_cfg enable block operation no disabled the block is disconnected from the gpio pins, p1[5] and p1[7]. (the pins may be used as general purpose io.) when the slave is enabled, the gpio pins are under control of the i 2 c hardware and are unavailable. all internal registers (except i2c_cfg) are held in reset. yes slave mode any external start condition causes the block to start receiving an address byte. regardless of the current state, any start resets the interface and initiates a receive operation. any stop causes the block to revert to an idle state [+] feedback
128 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c slave 15.3.10 i2c_scr register the i 2 c status and control register (i2c_scr) is used by the slave to control the flow of data bytes and to keep track of the bus state during a transfer. this register contains status bits to determine the state of the current i 2 c transfer, and control bits to determine the actions for the next byte transfer. at the end of each byte transfer, the i 2 c hardware interrupts the m8c microcontrol- ler and stalls the i 2 c bus on the subsequent low of the clock, until the psoc device intervenes with the next command. this register may be read as many times as necessary; but on a subsequent write to this register, the bus stall is released and the current transfer continues. there are five status bits: byte complete, lrb, address, stop status, and bus error. these bits have read/clear (rc) access, which means that they are set by hardware but may be cleared by a write of ?0? to the bit position. under cer- tain conditions, status is clear ed automatically by the hard- ware. there are two control bits: transmit and ack. these bits have rw access and may be cleared by hardware. bit 7: bus error. the bus error status detects misplaced start or stop conditions on the bus. these may be due to noise, rogue devices, or other devices that are not yet syn- chronized with the i 2 c bus traffic. according to the i 2 c spec- ification, all compatible devices must reset their interface upon a received start or stop. this is a natural thing to do in slave mode because a start initiates an address reception and a stop idles the slave. a bus error is defined as follows. a start is only valid if the block is idle or a slave receiver is ready to receive the first bit of a new byte after an ack. any other timing for a start con- dition sets the bus error bit. a stop is only valid if the block is idle or a slave receiver is ready to receive the first bit of a new byte after an ack. any other timing for a stop condition sets the bus error bit. bit 5: stop status. stop status is set upon detection of an i 2 c stop condition. this bit is sticky, which means that it remains set until a ?0? is written back to it by the firmware. this bit may only be cleared if the byte complete status bit is set. if the stop interrupt enable bit is set, an interrupt is also generated upon stop detection. it is never automatically cleared. using this bit, a slave can distinguish between a previous stop or restart upon a given address byte inter- rupt. the selections are shown in the following table: bit 4: ack. this control bit defines the acknowledge data bit that is transmitted out in response to a received byte. when receiv- ing, a byte complete interrupt is generated after the eighth data bit is received. upon the subsequent write to this regis- ter to continue (or terminate) the transfer, the state of this bit determines the next transmitted data bit. it is active high . a ?1? sends an ack and a ?0? sends a nack. a slave receiver sends a nack to inform the master that it cannot receive any more bytes. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,d7h i2c_scr bus error stop status ack address transmit lrb byte complete # : 00 legend # access is bit specific. bit access description 7 rc bus error 1 = a misplaced start or stop condition was detected. this status bit must be cleared by firmware with a write of ?0? to the bit position. it is never cleared by the hardware. 5 rc stop status 1 = a stop condition was detected. this status bit must be cleared by firmware with a write of ?0? to the bit position. it is never cleared by the hardware. 4 rw ack: acknowledge out 0 = nack the last received byte. 1 = ack the last received byte. this bit is automatically cleared by hardware upon the fol- lowing byte complete event. 3 rc address 1 = the transmitted or received byte is an address. this status bit must be cleared by firmware with a write of ?0? to the bit position. 2 rw transmit 0 = receive mode. 1 = transmit mode. this bit is set by firmware to define the direction of the byte transfer. any start detect automatically clears this bit. 1 rc lrb: last received bit the value of the ninth bit in a transmit sequence, which is the acknowledge bit from the receiver. 0 = last transmitted byte was ack?ed by the receiver. 1 = last transmitted byte was nack?ed by the receiver. any start detect automatically clears this bit. 0 rc byte complete transmit mode: 1 = 8 bits of data have been transmitted and an ack or nack has been received. receive mode: 1 = 8 bits of data have been received. any start detect automatically clears this bit. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 129 i2c slave bit 3: address. this bit is set when an address is received. this consists of a start or restart, and an address byte. in slave mode when this status is set, firmware reads the received address from the data register and compares it with its own address. if the address does not match, the firmware writes a nack indication to this register. no further interrupts occur until the next address is received. if the address does match, firmware must ack the received byte, then byte complete interrupts are generated on subsequent bytes of the transfer. when in i 2 c compatibility mode the address bit should not be cleared between a start and the next byte complete. if it is cleared during this time the start status is cleared inter- nally. bit 2: transmit. this bit sets the direction of the shifter for a subsequent byte transfer. the shifter is always shifting in data from the i 2 c bus, but a write of ?1? enables the output of the shifter to drive the sda output line. since a write to this register initiates the next transfer, data must be written to the data register before writing this bit. in receive mode, the pre- viously received data must have been read from the data register before this write. firmware derives this direction from the rw bit in the received slave address. this direction control is only valid for data transfers. the direction of address bytes is determined by the hardware. bit 1: lrb. last received bit. this is the last received bit in response to a previously transmitted byte. in transmit mode, the hardware sends a byte from the data register and clock in an acknowledge bit from the receiver. upon the sub- sequent byte complete interr upt, firmware checks the value of this bit. a ?0? is the ack value and a ?1? is a nack value. the meaning of lrb depends upon the current operating mode. ?0?: ack. the master wants to read another byte. the slave loads the next byte into the i2c_dr register and sets the transmit bit in the i2c_scr register to continue the transfer. ?1?: nack. the master is done reading bytes. the slave reverts to idle state on the subsequent i2c_scr write (regardless of the value written). bit 0: byte complete. the i 2 c hardware operates on a byte basis. in transmit mode, this bit is set and an interrupt is generated at the end of nine bits (the transmitted byte + the received ack). in receive mode, the bit is set after the eight bits of data are received. when this bit is set, an interrupt is generated at these data sampling points, which are associ- ated with the scl input clock rising (see details in timing diagrams on page 130 ). if the psoc device responds with a write back to this register before the subsequent falling edge of scl (which is approximately one-half bit time), the trans- fer continues without interruption. however, if the device cannot respond within that time, the hardware holds the scl line low, stalling the i 2 c bus. a subsequent write to the i2c_scr register releases the stall. for additional information, refer to the i2c_scr register on page 240 . 15.3.11 i2c_dr register the i 2 c data register (i2c_dr) provides read/write access to the shift register. bits 7 to 0: data[7:0]. this register is not buffered; there- fore, writes and valid data reads occur at specific points in the transfer. these cases are outlined as follows: slave receiver ? data in the i2c_dr register is only valid for reading when the byte complete status bit is set. data bytes must be read from the i2c_dr register before writing to the i2c_scr register , which continues the transfer. slave transmitter ? data bytes must be written to the i2c_dr register before the transmit bit is set in the i2c_scr register , which continues the transfer. for additional information, refer to the i2c_dr register on page 241 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,d8h i2c_dr data[7:0] rw : 00 [+] feedback
130 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c slave 15.4 timing diagrams 15.4.1 clock generation figure 15-6 illustrates the i 2 c input clocking scheme. the sysclk pin is an in put into a three-stage ripple divider that pro- vides the baud rate selections. when the block is disabled, all internal state is held in a reset state. when the enable bit in the i2c_cfg register is set, the reset is synchronously released and the clock generation is enabled. all three taps from the rip- ple divider are selectable (/2, /4, /8) from the clock rate bits in the i2c_cfg register . if any of the three divider taps is selected, that clock is resynchronized to sysclk. the resulting clock is routed to all of the synchronous elements in the design. figure 15-6. i 2 c input clocking 15.4.2 basic i/o timing figure 15-7 illustrates basic input/output timing that is valid for both 16 times sampling and 32 times sampling. for 16 times sampling, n=4; for 32 times samp ling, n=12. n is derived from th e half-bit rate sampling of eigh t and 16 clocks, respectively, minus the input latency of three (count of 4 and 12 correspond to 5 and 13 clocks). figure 15-7. basic input/output timing i/o write sysclk 4 2 8 two sysclks to first block clock. enable block reset resync clock default 8 scl scl_in clock sda_out clk ctr n 1 2 n 0 1 2 n 0 0 shift sda_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 131 i2c slave 15.4.3 status timing figure 15-8 illustrates the interrupt timing for byte complete, which occurs on the positive edge of the ninth clock (byte + ack/nack) in transmit mode and on the positive edge of the eighth clock in receive mode. there is a maximum of three cycles of latency due to the input synch ronizer/filter circuit. as shown, the interrupt occurs on the clock following a valid scl positive edge input transition (after the synchro- nizers). the address bit is set with the same timing but only after a slave address has been received. the lrb (last received bit) status is also set with the same timing but only on the ninth bit after a transmitted byte. figure 15-8. byte complete, address, lrb timing figure 15-9 shows the timing for stop status. this bit is set (and the interrupt occurs) two clocks after the synchronized and filtered sda line transitions to a ?1?, when the scl line is high. figure 15-9. stop status and interrupt timing figure 15-10 illustrates the timing fo r bus error interrupts. bus error status (and interrupt) occurs one cycle after the internal start or stop detect (two cycles after the filtered and synchronized sda input transition). figure 15-10. bus e rror interrupt timing 3 cycles latency clock transmit: ninth positive edge scl receive: eighth positive edge scl scl scl_in synchronized) irq max clock scl sda_in synchronized) stop irq and status sda top detect clock scl sda_in (synchronized) bus error and interrupt sda start detect misplaced start misplaced stop clock scl sda_in (synchronized) bus error and interrupt sda stop detect [+] feedback
132 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c slave 15.4.4 slave stall timing when a byte complete interrupt occurs, the psoc de vice firmware must respond with a write to the i2c_scr register to con- tinue the transfer (or terminate the tr ansfer). the interrupt occurs two clo cks after the rising edge of scl_in (see status tim- ing on page 131 ). as illustrated in figure 15-11 , firmware has until one clock after the falling edge of scl_in to write to the i2c_scr register ; otherwise, a stall occurs. after stalled, the i/o write releases the stall. the setup time between data output and the next rising edge of scl is always n-1 clocks. figure 15-11. slave stall timing 15.4.5 implementation the i2c block responds to transactions during sleep if and only if: a. the i2c slave block is enabled, i.e., bit 0 of the i2c_cfg register is set to 1'b1. b. if i2c_on is set or the usb enable bit of usb_cr0 is set. c. pd signal from the sleep controller is high. to enable the wakeup through i2c, set the hw addr en bit so that the i2c slave block wakes the system if and only if the address matches. figure 15-12 depicts the wakeup sequence through i2c. note the last step in this flowchart where scl is released in general, represents the configuration where buffer mode is enabled. figure 15-12. i2c wakeup sequence scl clock scl_in (synchronized) sda_out i/o write 1 clocks n-1 clocks stall no stall scl_out i2c sleep enabled? start detect device address matched? wakeup system by interrupt and pull the scl low ack the address byte and release the scl line once imo is operational send nack no yes yes no yes no [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 133 i2c slave 15.4.6 compatibility mode configuration in compatibility mode, the scl, as usual, is pulled low until the cpu responds by setting the transmit/receive bit and for loading a byte in the i2c_data register (in case of transmit operation) even though imo is operational. figure 15-13 illus- trates the process of switching from direct clocking to sampled mode. figure 15-13. direct clocking to sample mode timing see the following notes regarding figure 15-13 :. a. after, the address matches irq and a signal called switch_to_sample_mode are asserted asynchronously. b. this irq goes as input to the sleep controller block. the sleep controller block wakes the system by clearing the sleep bit. c. after imo is operational, the signal switch_to_sample_mode is registered and asserted high, indicating imo is opera- tional. when this registered signal becomes high, the switch_to_sample_mode signal deasserts asynchronously. d. the state machines and other logic are put at ap propriate states when switching to sample mode. imo rel_switch_sample_mode switch_to_sample_mode irq scl sda scl is released here if buffer mode is enabled, otherwise it is released once cpu is operational and responds by setting the transmit/receive bit. it thenloads the i2c_data register with a byte if it is a transmit operation 0 [+] feedback
134 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c slave [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 135 16. system resets this chapter discusses the system resets and their associated registers. psoc devices support several types of resets. the various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow for user supplied external reset, and to provide recovery from errant code operation. for a complete table of the system reset regis- ters, refer to the summary table of the system resource registers on page 106 . for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 16.1 architectural description when reset is initiated, all registers are restored to their default states. in the register reference chapter on page 187 , this is indicated by the por row in the register tables and elsewhere it is indicated in the access column values on the right side of the colon, in the register tables. minor exceptions are explained ahead. the following types of resets occur in the psoc device: power on reset (por). this occurs at low supply volt- age and is comprised of multiple sources. external reset (xres). this active high reset is driven into the psoc device on parts that contain an xres pin. watchdog reset (wdr). this optional reset occurs when the watchdog timer expires before being cleared by user firmware. watchdog resets default to off. internal reset (ires). this occurs during the boot sequence if the srom code determines that flash reads are invalid. the occurrence of a reset is recorded in the status and control registers (cpu_scr0 for por, xres, and wdr) or in the system status and control register 1 (cpu_scr1 for iress). firmware can inte rrogate these registers to determine the cause of a reset. 16.2 pin behavior during reset power on reset and external reset cause toggling on two gpio pins, p1[0] and p1[1], as described ahead and illus- trated in figure 16-1 and figure 16-2 . this allows program- mers to synchronize with the psoc device. all other gpio pins are placed in a high impedance state during and imme- diately following reset. 16.2.1 gpio behavior on power up at power up, the internal por causes p1[0] to initially drive a strong high (1) while p1[1] drives a resistive low (0). after 256 sleep oscillator cycles (approximately 8 ms), the p1[0] signal transitions to a resistive low state. after an additional 256 sleep oscillator clocks, both pins transition to a high impedance state and normal cpu operation begins. this is illustrated in the following figure. figure 16-1. p1[1:0] behavior on power up internal reset p1[0] p1[1] hiz hiz vdd por trip point s1 r0 r0 r0 t1 t2 t1 = t2 = 256 sleep clock cycles (approximately 8 ms) [+] feedback
136 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c system resets 16.2.2 powerup external reset behavior the device?s core runs on chip regulated supply, so there is a time delay in powering up the core. a short xres pulse at power up causes an external reset startup behavior. how- ever, the event is latched and applied only after the core has powered up (a delay of about 1 ms). 16.2.3 gpio behavior on external reset during external reset (xres=1), both p1[0] and p1[1] drive resistive low (0). after xres deasserts, these pins continue to drive resistive low for another eight sleep clock cycles (approximately 200 s). after this time, both pins transition to a high impedance state and normal cpu operation begins. this is illustrated in figure 16-2 . figure 16-2. p1[1:0] behavior on external reset (xres) xres p1[0] p1[1] hiz hiz r0 r0 t1 t1 = 8 sleep clock cycles (approximately 200 s) [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 137 system resets 16.3 register definitions the following registers are associated with the psoc system resets and are listed in address order. each register descrip- tion has an associated register table showing the bit structure for that register. the bits in the tables that are grayed out a re reserved bits and are not detailed in the register descriptions that follow. always write reserved bits with a value of 0. for a complete table of system rese t registers, refer to the ?summary table of the system resource registers? on page 106 . 16.3.1 cpu_scr1 register the system status and control register 1 (cpu_scr1) conveys the status and control of events related to internal resets and watchdog reset. bit 7: iress. internal reset status. this bit is a read only bit that determines if the booting process occurred more than once. when this bit is set, it indicates that the srom swbootre- set code executed more than once. if this bit is not set, the swbootreset executed only once. in either case, the swbootreset code does not allow execution from code stored in flash until the m8c core is in a safe operating mode with respect to supply voltage and flash operation. there is no need for concern when this bit is set. it is pro- vided for systems that may be sensitive to boot time, so that they can determine if the normal one-pass boot time was exceeded. for more information on the swbootreest code see the supervisory rom (srom) chapter on page 89 . bit 4:3 slimo[1:0]. these bits set the imo frequency range. see the table ahead for more information. these changes allow for optimization of speed and power. the imo trim value must also be changed when slimo is changed (see engaging slow imo on page 63 ). when not in external clocking mode, the imo is the source for sysclk; therefore, when the speed of the imo changes so does sysclk. bit 0: iramdis. initialize ram disable. this bit is a control bit that is readable and writeable. the default value for this bit is ?0?, which indicates that the maximum amount of sram must be initialized on watchdog reset to a value of 00h. when the bit is ?1?, the minimum amount of sram is initial- ized after a watchdog reset. for additional information, refer to the cpu_scr1 register on page 257 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access x,feh cpu_scr1 iress slimo[1:0] iramdis # : 0 legend x an ?x? before the comma in the address field indicates that this r egister can be read or written to no matter what bank is use d. # access is bit specific. refer to the register reference chapter on page 187 for additional information. slimo cy8ctmg20x, cy8ctst200 00 12 01 6 10 24 11 reserved [+] feedback
138 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c system resets 16.3.2 cpu_scr0 register the system status and control register 0 (cpu_scr0) is used to convey the status and control of events for various functions of a psoc device. bit 7: gies. global interrupt enable status. this bit is a read only status bit and its use is discouraged. the gies bit is a legacy bit that was used to provide the ab ility to read the gie bit of the cpu_f register. however, the cpu_f register is now readable. when this bit is set, it indicates that the gie bit in the cpu_f register is also set, which in turn, indicates that the microprocessor services interrupts. bit 5: wdrs. watchdog reset status. this bit may not be set. it is normally ?0? and automatically set whenever a watchdog reset occurs. the bit is readable and clearable by writing a ?0? to its bit position in the cpu_scr0 register. bit 4: pors. power on reset status. this bit, which is the watchdog enable bit, is set automatically by a por or exter- nal reset (xres). if the bit is cleared by user code, the watchdog timer is enabled. after cleared, the only way to reset the pors bit is to go through a por or xres. thus, there is no way to disable the watchdog timer other than to go through a por or xres. bit 3: sleep. this bit is used to enter low power sleep mode when set. to wake up the system, this register bit is cleared asynchronously by any enabled interrupt. there are two special features of this bit that ensure proper sleep oper- ation. first, the write to set the register bit is blocked if an interrupt is about to be taken on that instruction boundary (immediately after the write). second, there is a hardware interlock to ensure that, once set, th e sleep bit may not be cleared by an incoming interrupt until the sleep circuit has finished performing the sleep sequence and the system- wide power down signal has been asserted. this prevents the sleep circuit from being interrupted in the middle of the process of system power down, possibly leaving the system in an indeterminate state. bit 0: stop. this bit is readable and writeable. when set, the psoc m8c stops executing code until a reset event occurs. this can be either a por, wdr, or xres. if an application wants to stop code execution until a reset, the preferred method is to use the halt instruction rather than a register write to this bit. for additional information, refer to the cpu_scr0 register on page 258 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access x,ffh cpu_scr0 gies wdrs pors sleep stop # : xx legend # access is bit specific. refer to register detail for additional information. xx the reset value is 10h after por/xres and 20h after a watchdog reset. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 139 system resets 16.4 timing diagrams 16.4.1 power on reset a power on reset (por) is triggered whenever the supply voltage is below the por trip point. por ends once the sup- ply voltage rises above this voltage. refer to the por and lvd chapter on page 143 for more information on the opera- tion of the por block. por consists of two pieces: an imprecise por (ipor) and a precision por (ppor). ?por? refers to the or of these two functions. ipor has coarser accuracy and its trip point is typically lower than ppor?s trip point. ppor is derived from a circuit that is calibrated (during boot) for a very accu- rate location of the por trip point. during por (por=1), the imo is powered off for low power during startup. after por deasserts, the imo is started (see figure 16-4 ). por configures register reset status bits as shown in 16.4.4 reset details on page 141 . 16.4.2 external reset an external reset (xres) is caused by pulling the xres pin high. the xres pin has an always-on, pull down resis- tor, so it does not require an external pull down for operation and can be tied directly to ground or left open. behavior after xres is similar to por. during xres (xres=1), the imo is powered off for low power during startup. after xres deasserts, the imo is started (see figure 16-4 ). how the xres configures register reset status bits is shown in 16.4.4 reset details on page 141 . 16.4.3 watchdog timer reset the user has the option to enable the watchdog timer reset (wdr), by clearing the pors bit in the cpu_scr0 register. after the pors bit is cleared, the watchdog timer cannot be disabled. the only exception to this is if a por/ xres event takes place, which disables the wdr. note that a wdr does not clear the watchdog timer. see watchdog timer on page 81 for details of the watchdog operation. when the watchdog timer expires, a watchdog event occurs, resulting in the reset sequence. some characteristics unique to the wdr are as follows. psoc device reset asserts for one cycle of the clk32k clock (at its reset state). the imo is not halted during or after wdr (that is, the part does not go through a low power phase). cpu operation re-starts one clk32k cycle after the internal reset deasserts (see figure 16-3 ). how the wdr configures register reset status bits is shown in 16.4.4 reset details on page 141 . figure 16-3. key signals during wdr clk32 reset sleep timer imo pd imo (not to scale) cpu reset 0 1 2 n=2048 ires : reset 1 cycle, then 2048 additional cycles low power hold-off, and then 1 cycle with imo on before the cpu reset is released. wdr : reset 1 cycle, then one additional cycle before the cpu reset is released. imo pd imo (not to scale) cpu reset (stays low) reset sleep timer 0 12 clk32 [+] feedback
140 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c system resets figure 16-4. key signals during por and xres imo pd imo (not to scale) cpu reset por (ipor followed by ppor): reset while por is high (imo off), then 511(+) cycles (imo on), and then the cpu reset is released. xres is the same, with n=8. clk32 reset sleep timer 0 01511 n=512 (follows por / xres) imo pd imo (not to scale) cpu reset ppor (with no ipor): reset while ppor is high and to the end of the next 32k cycle (imo off); 1 cycle imo on before the cpu reset is released. note that at the 3v level, ppor tends to be brief because the reset clears the por range register (vlt_cr) back to the default 2.4v setting. clk32 ppor sleep timer 0 12 reset ipor ppor imo pd imo (not to scale) cpu reset xres : reset while xres is high (imo off), t hen 7(+) cycles (imo on), and then the cpu reset is released. clk32 reset sleep timer 127 8 xres 0 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 141 system resets 16.4.4 reset details timing and functionality details are summarized in ta b l e 1 6 - 1 . figure 16-4 on page 140 shows some of the relevant signals for ipor, ppor, xres, and wdr. 16.5 power modes the ilo block drives the clk32k clock used to time most events during the reset sequence. this clock is powered down by ipor but not by any other reset. the sleep timer provides interval timing. while por or xres assert, the imo is powered off to reduce startup power consumption. during and following ires (for 64 ms nominally), the imo is powered off for low average power during slow supply ramps. during and after por or xres, the bandgap circuit is pow- ered up. the imo is always on for at least one clk32k cycle before cpu reset is deasserted. table 16-1. reset functionality item ipor (part of por) ppor (part of por) xres wdr reset length while por=1 while ppor=1, plus 30-60 s (1-2 clocks) while xres=1 30 s (1 clock) low power (imo off) during reset? yes yes yes no low power wait following reset? no no no no clk32k cycles from end of reset to cpu reset deasserts a a. cpu reset is released after synchronization with the cpu clock. 512 1 8 1 register reset (see next line for cpu_scr0, cpu_scr1) all all, except ppor does not reset bandgap trim register all all reset status bits in cpu_scr0, cpu_scr1 set pors, clear wdrs, clear iramdis set pors, clear wdrs, clear iramdis set pors, clear wdrs, clear iramdis clear pors, set wdrs, iramdis unchanged bandgap power on on on on boot time b b. measured from cpu reset release to execution of the code at flash address 0x0000. 2.2 ms 2.2 ms 2.2 ms 2.2 ms [+] feedback
142 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c system resets [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 143 17. por and lvd this chapter briefly discusses the power on reset (por) and low voltage detect (lvd) circuits and their associated regis- ters. for a complete table of the por registers, refer to the summary table of the system resource registers on page 106 . for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 17.1 architectural description the power on reset (por) and low voltage detect (lvd) circui ts provide protection against low voltage conditions. the por function senses vcc and vcore (regulated voltage) holdi ng the system in reset until the magnitude of vcc and vcore supports operation to specification. the lvd function sens es vcc and provides an interrupt to the system when vcc falls below a selected threshold. other outputs and status bits are provided to indicate important voltage trip levels. refer to sec- tion 16.2 pin behavior during reset for a description of gpio pin behavior during power up. [+] feedback
144 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c por and lvd 17.2 register definitions the following registers are associated with the por and lvd, and are listed in address order. the register descriptions below have an associated register table showing the bit structure. the bi ts that are grayed out in the register tables are reserved b its and are not detailed in the register descriptions that follow. reserved bits must always be written with a value of ?0?. for a complete table of the por registers, refer to the summary table of the system resource registers on page 106 . 17.2.1 vlt_cr register the voltage monitor control register (vlt_cr) sets the trip points for por, mon1 and lvd. the vlt_cr register is cleared by all resets. this can cause reset cycling during very slow s upply ramps to 5v when the mon1 range is set for the 5v range. this is because the reset clears the mon1 range setting back to 1.8v and a new boot or startup occurs (possibly many times). you can man- age this with sleep mode or reading voltage status bits if such cycling is an issue. bits 5 and 4: porlev[1:0]. these bits set the vcc level at which ppor switches to one of three valid values. do not use 11b because it is reserved. see the ?dc por and lvd specifications? table in the elec- trical specifications section of the psoc device data sheet for voltage tolerances for each setting. bit 3: lvdtben. this bit is and?ed with lvd to produce a throttle back signal that reduces cpu clock speed when low voltage conditions are detected. when the throttle back sig- nal is asserted, the cpu speed bits in the osc_cr0 regis- ter are reset, forcing the cpu speed to its reset state. bits 2 to 0: vm[2:0]. these bits set the vdd level at which the lvd comparator switches. see the ?dc por and lvd specifications? table in the elec- trical specifications section of the psoc device data sheet for voltage tolerances for each setting. for additional information, refer to the vlt_cr register on page 279 . 17.2.2 vlt_cmp register the voltage monitor comparators register (vlt_cmp) reads the state of internal supply voltage monitors. bit 1: lvd. this bit reads the state of the lvd comparator. zero vdd is above the trip point. the trip points for lvd are set by vm[2:0] in the vlt_cr register. for additional information, refer to the vlt_cmp register on page 280 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,e3h vlt_cr porlev[1:0] lvdtben vm[2:0] rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,e4h vlt_cmp lvd rw : 0 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 145 18. spi this chapter presents the serial peripheral interconnect (spi) and its associated registers. for a complete table of the spi registers, refer to the summary table of the system resource registers on page 106 . for a quick reference of all psoc reg- isters in address order, refer to the register reference chapter on page 187 . 18.1 architectural description the serial peripheral interconnect (spi) block is a dedi- cated master or slave spi. the spi slave function requires three inputs: clock, data, and ss_ (unless the ss_ is forced active with the ss_bit in the configuration register). figure 18-1. spi block diagram 18.1.1 spi protocol function the spi is a motorola? specification for implementing full- duplex synchronous serial communication between devices. the 3-wire protocol uses both edges of the clock to enable synchronous communication without the need for stringent setup and hold requirements. figure 18-2 shows the basic signals in a simple connection. figure 18-2. basic spi configuration a device can be a master or slave. a master outputs clock and data to the slave device and inputs slave data. a slave device inputs clock and data from the master device and outputs data for input to the master. together, the master and slave are essentially a circular shift register, where the master generates the clocking and initiates data transfers. a basic data transfer occurs when the master sends eight bits of data, along with eight clocks. in any transfer, both master and slave transmit and receive simultaneously. if the master only sends data, the received data from the slave is ignored. if the master wishes to receive data from the slave, the master must send dummy bytes to generate the clocking for the slave to send data back. spi block registers sysclk data_out data_in clk_in clk_out int ss_ sclk mosi, miso sclk mosi, miso configuration[7:0] control[7:0] transmit[7:0] receive[7:0] spi master spi slave mosi sclk ss_ miso mosi miso sclk data is output by both the master and slave on one edge of the clock. data is registered at the input of both devices on the opposite edge of the clock. mosi sclk ss_ miso [+] feedback
146 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi 18.1.1.1 spi protocol signal definitions the spi protocol signal definitions are located in table 18-1 . the use of the ss_ signal varies according to the capability of the slave device. 18.1.2 spi master function the spi master (spim) offers spi operating modes 0-3. by default, the most significant bit (msb) of the data byte is shifted out first. an additional option can be set to reverse the direction and shift the data byte out the least significant bit (lsb) first. (refer to the timing diagrams for this function on page 152 .) when configured for spim, dr0 functions as a shift register with input from the data input (miso) and output to the pri- mary output f1 (mosi). dr1 is the tx buffer register and dr2 is the rx buffer register. the spi protocol requires data to be registered at the device input, on the opposite edge of the clock that operates the output shifter. an additional register (rxd), at the input to the dr0 shift register, has been implemented for this pur- pose. this register stores received data for one-half cycle before it is clocked into the shift register. the spim controls data transmission between master and slave because it generates the bit clock for internal clocking and for clocking the spis. the bit clock is derived from the clk input selection. there are four control bits and four status bits in the control register (spi_cr) that provide for device interfacing and synchronization. the spim hardware has no supp ort for driving the slave select (ss_) signal. the behavior and use of this signal is application and device dependent and, if required, must be implemented in firmware. 18.1.2.1 usability exceptions the following are usability exceptions for the spi protocol function. the spi_rxr (rx buffer) register is not writeable. the spi_txr (tx buffer) register is not readable. 18.1.2.2 block interrupt the spim block has a selection of two interrupt sources: interrupt on tx reg empty (default) or interrupt on spi complete. mode bit 1 in the function register controls the selection. these modes are discussed in detail in spim tim- ing on page 152 . if spi complete is selected as the block interrupt, the con- trol register must be read in the interrupt routine so that this status bit is cleared; otherwise, no subsequent interrupts are generated. 18.1.3 spi slave function the spi slave (spis) offers spi operating modes 0-3. by default, the msb of the data byte is shifted out first. an addi- tional option can be set to reverse the direction and shift the data byte out lsb first. (refer to the timing diagrams for this function on page 157 .) the spi protocol requires data to be registered at the device input, on the opposite edge of the clock that operates the output shifter. an additional register (rxd), at the input to the dr0 shift register, is implemented for this purpose. this register stores received data for one-half cycle before it is clocked into the shift register. the spis function derives all clocking from the sclk input (typically an external spi master). this means that the mas- ter must initiate all transmissions. for example, to read a byte from the spis, the master must send a byte. there are four control bits and four status bits in the control register (spi_cr) that provide for device interfacing and synchronization. there is an additional data input in the spis, slave select (ss_), which is an active low signal. ss_ must be asserted to enable the spis to receive and transmit. ss_ has two high level functions: 1) to allow for the selection of a given slave in a multi-slave environment, and 2) to provide addi- tional clocking for tx data queuing in spi modes 0 and 1. ss_ may be controlled from an external pin or can be con- trolled by way of user firmware. when ss_ is negated, the spis ignores any mosi/sclk input from the master. in addition, the spis state machine is reset and the miso output is forced to idle at logic 1. this allows for a wired-and connection in a multi-slave environ- ment. note that if high z output is required when the slave is not selected, this behavior must be implemented in firmware with i/o writes to the port drive register. 18.1.3.1 usability exceptions the following are usability exceptions for the spi slave function. the spi_rxr (rx buffer) register is not writeable. the spi_txr (tx buffer) register is not readable. table 18-1. spi protocol signal definitions name function description mosi master out slave in master data output. miso master in slave out slave data output. sclk serial clock clock generated by the master. ss_ slave select (active low) this signal is provided to enable multi-slave con- nections to the miso pin. the mosi and sclk pins can be connected to multiple slaves, and the ss_ input selects which slave receives the input data and drives the miso line. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 147 spi 18.1.3.2 block interrupt the spis block has a selection of two interrupt sources: interrupt on tx reg empty (default) or interrupt on spi complete (same selection as the spim). mode bit 1 in the function register controls the selection. if spi complete is selected as the block interrupt, the con- trol register must still be read in the interrupt routine so that this status bit is cleared; otherwise, no subsequent inter- rupts are generated. 18.1.4 input synchronization all pin inputs are double synchronized to sysclk by default. synchronization can be bypassed by setting the byps bit in the spi_cfg register. 18.2 register definitions the following registers are associated with the spi and are listed in address order. the register descriptions have an associ- ated register table showing the bit structure for that register. for a complete table of spi registers, refer to the summary table of the system resource registers on page 106 . data registers 18.2.1 spi_txr register the spi transmit data register (spi_txr) is the spi?s transmit data register. bits 7 to 0: data[7:0]. these bits encompass the spi transmit register. they are di scussed by function type in table 18-2 and ta b l e 1 8 - 3 . for additional information, refer to the spi_txr register on page 190 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,29h spi_txr data[7:0] w : 00 [+] feedback
148 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi 18.2.2 spi_rxr register the spi receive data register (spi_rxr) is the spi?s receive data register. a write to this register clears the rx reg full status bit in the control register (spi_cr). bits 7 to 0: data[7:0]. these bits encompass the spi receive register. they are discussed by function type in table 18-2 and table 18-3 . for additional informat ion, refer to the spi_rxr register on page 191 . 18.2.2.1 spi master data register definitions there are two 8-bit data registers and one 8-bit control/status register. table 18-2 explains the meaning of the transmit and receive registers in the context of spim operation. 18.2.2.2 spi slave data register definitions there are two 8-bit data registers and one 8-bit control/status register. table 18-3 explains the meaning of the transmit and receive registers in the context of spis operation. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,2ah spi_rxr data[7:0] r : 00 table 18-2. spim data register descriptions name function description spi_txr tx buffer write only register. if no transmission is in progress and this register is written to , the data from this register is loaded into the shift registe r on the following clock edge, and a transmission is initiated. if a tr ansmission is currently in prog ress, this register serves as a buffer for tx data. this register must only be written to when tx reg empty status is set and the write clears the tx reg empty status bit in the control register. when the data is transferred from this register to the shift register, then tx reg empty status is set. spi_rxr rx buffer read only register. when a byte transmission/reception is complete, the data in the shifter is transferred into the rx buffer register and rx reg full status is set in the control register. a read from this register clears the rx reg full status bit in the control register. table 18-3. spis data register descriptions name function description spi_txr tx buffer write only register. this register must only be written to when tx reg empty status is set and the write clears the tx reg empty status bit in the control register. when the data is transferred from this regist er to the shift register, then tx reg empty status is set. spi_rxr rx buffer read only register. when a byte transmission/reception is complete, the data in the shifter is transferred into the rx buffer register and rx reg full status is set in the control register. a read from this register clears the rx reg full status bit in the control register. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 149 spi control register 18.2.3 spi_cr register the spi control register (spi_cr) is the spi?s control reg- ister. bit 7: lsb first. this bit determines how the serial data is shifted out, either lsb or msb first. bit 6: overrun. this status bit indicates whether or not there was a receive buffer overrun. a read from the receive buffer after each received byte must be performed before the reception of the next byte in order to avoid an overrun condition. bit 5: spi complete. this status bit indicates the comple- tion of a transaction. a read from this register clears this bit. bit 4: tx reg empty. this status bit indicates whether or not the transmit register is empty. bit 3: rx reg full. this status bit indicates a receive reg- ister full condition. bit 2: clock phase. this bit determines the edge (rising or falling) on which the data changes. bit 1: clock polarity. this bit determines the logic level the clock codes to in its idle state. bit 0: enable. this bit enables the spi block. for additional information, refer to the spi_cr register on page 192 . 18.2.3.1 spi control register definitions address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,2bh spi_cr lsb first overrun spi complete tx reg empty rx reg full clock phase clock polarity enable # : 00 legend # access is bit specific. refer to the register detail for additional information. table 18-4. spi control register descriptions bit # name access description 7 lsb first read/write 0 = data shifted out msb first. 1 = data shifted out lsb first. 6 overrun read only 0 = no overrun. 1 = indicates new byte received before previous one is read. 5 spi complete read only 0 = transaction in progress. 1 = transaction is complete. reading spi_cr clears this bit. 4 tx reg empty read only 0 = tx register is full. 1 = tx register is empty. writing spi_txr register clears this bit. 3 rx reg full read only 0 = rx register is not full. 1 = rx register is full. reading spi_rxr register clears this bit. 2 clock phase read/write 0 = data changes on trailing edge. 1 = data changes on leading clock edge. 1 clock polarity read/write 0 = non-inverted, clock idles low (modes 0, 2). 1 = inverted, clock idles high (modes 1, 3). 0 enable read/write 0 = disable spi function. 1 = enable spi function. [+] feedback
150 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi configuration register the configuration block contains 1 register. this register must not be changed while the block is enabled. note that the spi configuration register is located in bank 1 of the psoc device?s memory map. 18.2.4 spi_cfg register the spi configuration register (spi_cfg) is used to con- figure the spi. bits 7 to 5: cl ock sel [2:0]. clock selection. these bits determine the operating frequency of the spi master. bit 4: bypass. this bit determines whether or not the inputs are synchronized to sysclk. bit 3: ss_. slave select. this bit determines the logic value of the ss_ signal when the ss_en_ signal is asserted (ss_en_ = 0). bit 2: ss_en_. slave select enable. this active low bit determines if the slave select (ss_) signal is driven inter- nally. if it is driven internally , its logic level is determined by the ss_ bit. if it is driven externally, its logic level is deter- mined by the external pin. bit 1: int sel. interrupt select. this bit selects which condi- tion produces an interrupt. bit 0: slave. this bit determines whether the block func- tions as a master or slave. for additional informat ion, refer to the spi_cfg register on page 261 . 18.2.4.1 spi configuration register definitions 18.2.5 related registers io_cfg1 register on page 272. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,29h spi_cfg clock sel[2:0] bypass ss_ ss_en_ int sel slave rw : 00 table 18-5. spi configuration register descriptions bit # name access mode description 7:5 clock sel read/write master sysclk 000b / 2 001b / 4 010b / 8 011b / 16 100b / 32 101b / 64 110b / 128 111b / 256 4 bypass read/write master/slave 0 = all pin inputs are doubled, synchronized. 1 = input synchronization is bypassed. 3 ss_ read/write slave 0 = slave selected. 1 = slave selection is determined from external ss_ pin. 2 ss_en_ read/write slave 0 = slave selection determined from ss_ bit. 1 = slave selection determined from external ss_ pin. 1 int sel read/write master/slave 0 = interrupt on tx reg empty. 1 = interrupt on spi complete. 0 slave read/write master/slave 0 = operates as a master. 1 = operates as a slave. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 151 spi 18.3 timing diagrams 18.3.1 spi mode timing figure 18-3 shows the spi modes that are typically defined as 0, 1, 2, or 3. these mode numbers are an encoding of two control bits: clock phase and clock polarity. clock phase indicates the relationship of the clock to the data. when the clock phase is '0', it means that the data is registered as an input on the leading edge of the clock and the next data is output on the trailing edge of the clock. when the clock phase is '1', it means that the next data is output on the leading edge of the clock and that data is reg- istered as an input on the trailing edge of the clock. clock polarity controls clock inversion. when clock polarity is set to '1?, the clock idle state is high. figure 18-3. spi mode timing mode 2, 3 (phase=1) output on leading edge. input on trailing edge. sclk, polarity=0 (mode 2) mosi miso sclk, polarity=1 (mode 3) 765 43210 mode 0, 1 (phase=0) input on leading edge. output on trailing edge. sclk, polarity=0 (mode 0) mosi miso sclk, polarity=1 (mode 1) 765 43210 ss_ ss_ [+] feedback
152 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi 18.3.2 spim timing enable/disable operation. as soon as the block is config- ured for spim, the primary output is the msb or lsb of the shift register, depending on the lsb first configuration in bit 7 of the control register. the auxiliary output is '1' or '0', depending on the idle clock state of the spi mode. this is the idle state. clock generation. figure 18-4 illustrates the spim input clocking scheme. the sysclk pi n is an input into an eight- stage ripple divider that provides the baud rate selections. when the block is disabled, all internal state is held in a reset state. when the enable bit in the spi_cr register is set, the reset is synchronously released and the clock generation is enabled. all eight taps from the ripple divider are selectable (/2, /4, /8, /16, /32, /64, /128, /256) from the clock sel bits in the spi_cfg register. the selected divider tap is resynchro- nized to sysclk. the resulting clock is routed to all of the synchronous elements in the design. when the block is disabled, the sclk and mosi outputs revert to their idle state. all internal state is reset (including cr0 status) to its configuration-specific reset state, except for dr0, dr1, and dr2, which are unaffected. figure 18-4. spi input clocking io write sysclk 4 2 8 two sysclks to first block clock. enable block reset resync clock default 2 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 153 spi normal operation. typical timing for an spim transfer is shown in figure 18-5 and figure 18-6 . the user initially writes a byte to transmit when tx reg empty status is true. if no transmission is currently in progress, the data is loaded into the shifter and the transmi ssion is initiated. the tx reg empty status is asserted again and the user is allowed to write the next byte to be transmitted to the tx buffer regis- ter. after the last bit is output, if tx buffer data is available with one-half clock setup time to the next clock, a new byte trans- mission is initiated. an spim block receives a byte at the same time that it sends one. the spi complete or rx reg full can be used to determine when the input byte has been received. figure 18-5. typical spim timing in mode 0 and 1 internal clock tx reg empty d7 mosi d6 d5 d2 d1 d0 d7 user writes first byte to the tx buffer register. shifter is loaded with first byte. user writes next byte to the tx buffer register. sclk (mode 0) shifter is loaded with next byte. last bit of received data is valid on this edge and is latched into rx buffer. clk input free running, internal bit rate clock is clk input divided by two. setup time for tx buffer write. sclk (mode 1) rx reg full first input bit is latched. first shift. [+] feedback
154 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi figure 18-6. typical spim timing in mode 2 and 3 status generation and interrupts. there are four status bits in an spi block: tx reg empty, rx reg full, spi com- plete, and overrun. tx reg empty indicates that a new byte can be written to the tx buffer register. when the block is enabled, this status bit is immediately asserted. this status bit is cleared when the user writes a byte of data to the tx buffer register. tx reg empty is a control input to the state machine and, if a transmission is not already in progress, the assertion of this control signal initiates one. this is the default spim block interrupt. however, an initial interrupt is not generated when the block is enabled. the user must write a byte to the tx buffer register and that byte must be loaded into the shifter before interrupts generated from the tx reg empty status bit are enabled. rx reg full is asserted on the edge that captures the eighth bit of receive data. this status bit is cleared when the user reads the rx buffer register (dr2). spi complete is an optional interrupt and is generated when eight bits of data and clock have been sent. in modes 0 and 1, this occurs one-half cycl e after rx reg full is set; because in these modes, data is latched on the leading edge of the clock a nd there is an addit ional one-half cycle remaining to complete that clock. in modes 2 and 3, this occurs at the same edge that the receive data is latched. this signal may be used to read the received byte or it may be used by the spim to disable the block after data trans- mission is complete. internal clock tx reg empty d7 mosi d6 d5 d2 d1 d0 d7 user writes first byte to the tx buffer register. shifter is loaded with the first byte. user writes next byte to the tx buffer register. sclk (mode 2) shifter is loaded with the next byte. last bit of received data is valid on this edge and is latched into rx buffer. clk input free running, internal bit rate clock is clk input divided by two. setup time for the tx buffer write. sclk (mode 3) rx reg full first input bit is latched. first shift. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 155 spi overrun status is set if rx reg full is still asserted from a previous byte when a new byte is about to be loaded into the rx buffer register. because the rx buffer register is imple- mented as a latch, overrun status is set one-half bit clock before rx reg full status. see figure 18-7 and figure 18-8 for status timing relation- ships. figure 18-7. spi status timing for modes 0 and 1 sclk (mode 1) sclk (mode 0) ss forced low ss toggled on a message basis ss toggled on each byte s s transfer in progress sclk (mode 1) sclk (mode 0) s s transfer in progress transfer in progress sclk (mode 1) sclk (mode 0) s s transfer in progress transfer in progress [+] feedback
156 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi figure 18-8. spi status timing for modes 2 and 3 mode 2, 3 (phase=1) output on leading edge. input on trailing edge. sclk, polarity=0 (mode 2) mosi miso sclk, polarity=1 (mode 3) 765 43210 ss_ tx reg empty rx reg full spi complete overrun overrun occurs one- half cycle before the last bit is received. last bit of byte is received. all clocks and data for this byte completed. tx buffer is transferred into the shifter. 7 765 43210 7 tx buffer is transferred into the shifter. user writes the next byte. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 157 spi 18.3.3 spis timing enable/disable operation. as soon as the block is config- ured for spi slave and before enabling, the miso output is set to idle at logic 1. the enable bit must be set and the ss_ asserted (either driven external ly or forced by firmware pro- gramming) for the block to output data. when enabled, the primary output is the msb or lsb of the shift register, depending on the lsb first configuration in bit 7 of the con- trol register. the auxiliary output of the spis is always forced into tristate. since the spis has no internal clock, it must be enabled with setup time to any external master supplying the clock. setup time is also required for a tx buffer register write before the first edge of the clock or the first falling edge of ss_, depending on the mode. this setup time must be assured through the protocol and an understanding of the timing between the master and slave in a system. when the block is disabled, the miso output reverts to its idle 1 state. all internal state is reset (including cr0 status) to its configuration-specific reset state, except for dr0, dr1, and dr2, which are unaffected. normal operation. typical timing for an spis transfer is shown in figure 18-9 and figure 18-10 . if the spis is prima- rily being used as a receiver, the rx reg full (polling only) or spi complete (polling or interrupt) status may be used to determine when a byte has been received. in this way, the spis operates identically with the spim. however, there are two main areas in which the spis operates differently: 1) spis behavior related to the ss_ signal, and 2) tx data queuing (loading the tx buffer register). figure 18-9. typical spis timing in modes 0 and 1 sclk (internal) tx reg empty d7 miso d6 d5 d2 d1 d0 user writes first byte to the tx buffer register in advance of transfer. at the falling edge of ss_, miso transitions from an idle (high) to output the first bit of data. user writes the next byte to the tx buffer register. sclk (mode 0) last bit of received data is valid on this edge and is latched into the rx buffer register. sclk (mode 1) ss_ rx reg full first input bit is latched. first shift. d7 d6 d7 [+] feedback
158 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi figure 18-10. typical spis timing in modes 2 and 3 slave select (ss_, active low). slave select must be asserted to enable the spis for receive and transmit. there are two ways to do this: drive the auxiliary input from a pin (selected by the aux i/o select bits in the output register). this gives the spi master control of the slave selection in a multi-slave environment. ss_ may be controlled in firmware with register writes to the output register. when aux i/o enable = 1, aux i/o select bit 0 becomes the ss_ input. this allows the user to save an input pin in single-slave environments. when ss_ is negated (whether from an external or internal source), the spis state machine is reset and the miso out- put is forced to idle at logic 1. in addition, the spis ignores any incoming mosi/sclk input from the master. status generation and interrupts. there are four status bits in the spis block: tx reg empty, rx reg full, spi complete, and overrun. the timing of these status bits are identical to the spim, with the exception of tx reg empty, which is covered in the section on tx data queuing. status clear on read. refer to the same subsection in spim timing on page 152 . tx data queuing. most spi applications call for data to be sent back from the slave to the master. writing firmware to accomplish this requires an understanding of how the shift register is loaded from the tx buffer register. all modes use the following mechanism: 1) if there is no transfer in progress, 2) if the shifter is empty, and 3) if data is available in the tx buffer register, the byte is loaded into the shifter. the only difference between the modes is that the definition of ?transfer in progress? is s lightly different between modes 0 and 1, and modes 2 and 3. sclk (internal) tx reg empty d7 miso d6 d5 d2 d1 d0 d7 user writes the first byte to the tx buffer register. shifter is loaded with first byte (by leading edge of the sclk). user writes the next byte to the tx buffer register. sclk (mode 2) shifter is loaded with the next byte. last bit of received data is valid on this edge and is latched into the rx buffer register. sclk (mode 3) rx reg full first input bit latched. first shift. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 159 spi figure 18-11 illustrates tx data loading in modes 0 and 1. a transfer in progress is defined to be from the falling edge of ss_ to the point at which the rx buffer register is loaded with the received byte. this means that to send a byte in the next trans - fer, it must be loaded into the tx buffer register before the falling edge of ss_. this ensures a minimum setup time for the first bit, since the leading edge of the first sclk must latch in the received data. if ss_ is not toggled between each byte or is forced low through the configuration register, the leading edge of sclk is used to define the start of transfer. however, in th is case, the user must provide the required setup time (one-half clock minimum before the leading edge) with a knowledge of system latencies and response times. figure 18-11. mode 0 and 1 transfer in progress figure 18-12 illustrates tx data loading in modes 2 and 3. in this ca se, a transfer in progress is defined to be from the leading edge of the first sclk to the point at which the rx buffer regi ster is loaded with the received byte. loading the shifter by th e leading edge of the clock has the effect of providing the require d one-half clock setup time, as the data is latched into the receiver on the trailing edge of the sclk in these modes. figure 18-12. mode 2 and 3 transfer in progress sclk (mode 1) sclk (mode 0) ss forced low ss toggled on a message basis ss toggled on each byte ss transfer in progress sclk (mode 1) sclk (mode 0) ss transfer in progress transfer in progress sclk (mode 1) sclk (mode 0) ss transfer in progress transfer in progress sclk (mode 3) sclk (mode 2) transfer in progress (no dependance on ss) [+] feedback
160 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 161 19. programmable timer this chapter presents the programmable timer and its associated registers. for a complete table of the programmable timer registers, refer to the summary table of the system resource registers on page 106 . for a quick reference of all psoc reg- isters in address order, refer to the register reference chapter on page 187 . 19.1 architectural description the device has three programmable timers (timer0, timer1, timer2). all three timers are individually con- trolled. the programmable timers are 16-bit down counters for the device. timer0 has a terminal count output. the tim- ers have one configuration and two data registers associ- ated with them. you start these timers by setting the start bit in their configuration registers (pt0_cfg, pt1_cfg, pt2_cfg). when started, the timers always start counting down from the value loaded into their data registers (pt*_data1, pt*_data0). the timers have a one-shot mode, in which the timers complete one full count cycle and stop. in one-shot mode the start bit in the configuration register is cleared after comp letion of one full count cycle. setting the start bit restarts the timer. figure 19-1. programmable timer block diagram 19.1.1 operation when started, the programmable timer loads the value con- tained in its data registers and counts down to its terminal count of zero. the timers output an active high terminal count pulse for one clock cycle upon reaching the terminal count. the low time of the terminal count pulse is equal to the loaded decimal count value, multiplied by the clock period (tc pw = count value decimal * clk period ). the period of the terminal count output is the pulse width of the terminal count, plus one clock period (tc period = tc pw + clk period ). refer to figure 19-2 and figure 19-3 . only timer0 outputs this terminal count output. timer1 and timer2 do not have a terminal count output. the timers work on either the 32 khz clock or cpu clock. this clock selection is done using the clksel bits in the respective configuration registers (pt0_cfg, pt1_cfg, pt2_cfg). make clock selections before setting the start bit so that the timing is not affected and clock frequency does not change while the timer is running. timer1 works on prescaled imo clock (imo-p) when the csd_mode bit in the cs_cr0 (0,a0) register is set to ?1?. timer1 outputs the start signal, which used in the true- touch module during csd mode. refer to 11.1.1.5 sigma delta on page 89 for more details on truetouch csd mode. when csd_mode is set to ?0?, it works on either the 32 khz clock or cpu clock, depending on the clksel bit setting. registers 32 khz clock/ cpu clock programmable timer configuration[7:0] data[7:0] data[7:0] terminal count [+] feedback
162 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c programmable timer figure 19-2. continuous operation example figure 19-3. one-shot operation example ptdata1 ptdata0 clock start one shot 00h 00h 03h 02h 01h 00h 03h 02h 01h 00h 03h 02h 01h count tc 0003h irq tc period tc period clock start one shot 00h 00h 03h 02h 01h count tc irq ptdata1 ptdata0 0003h tc period [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 163 programmable timer 19.2 register definitions the following registers are associated with the programmable ti mer and are listed in address order. the register descriptions have an associated register table showing the bit structure for t hat register. the bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow. reserved bits must always be written with a value of ?0?. for a complete table of programmable timer registers, refer to the summary table of the system resource registers on page 106 . 19.2.1 pt0_cfg register the programmable timer configuration register (pt0_cfg) configures the psoc?s programmable timer. bit 2: clksel. this bit determines if the timer runs on the 32 khz clock or cpu clock. if the bit is set to 1'b1, the timer runs on the cpu clock, otherwise, the timer runs on the 32 khz clock. bit 1: one shot. this bit determines if the timer runs in one-shot mode or continuous mode. in one-shot mode the timer completes one full count cycle and terminates. upon termination, the start bit in this register is cleared. in con- tinuous mode, the timer reloads the count value each time upon completion of its count cycle and repeats. bit 0: start. this bit starts the timer counting from a full count. the full count is determined by the value loaded into the data registers. this bit is cleared when the timer is run- ning in one-shot mode upon completion of a full count cycle. for additional information, refer to the pt0_cfg register on page 221 . 19.2.2 pt1_cfg register the programmable timer configuration register (pt1_cfg) configures the psoc?s programmable timer. bit 2: clksel. this bit determines if the timer runs on the 32 khz clock or cpu clock. if the bit is set to 1'b1, the timer runs on the cpu clock, otherwise, the timer runs on the 32 khz clock. bit 1: one shot. this bit determines if the timer runs in one-shot mode or continuous mode. in one-shot mode the timer completes one full count cycle and terminates. upon termination, the start bit in this register is cleared. in con- tinuous mode, the timer reloads the count value each time upon completion of its count cycle and repeats. bit 0: start. this bit starts the timer counting from a full count. the full count is determined by the value loaded into the data registers. this bit is cleared when the timer is run- ning in one-shot mode upon completion of a full count cycle. for additional information, refer to the pt1_cfg register on page 224 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,b0h pt0_cfg clksel one shot start rw : 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,b3h pt1_cfg clksel one shot start rw : 0 [+] feedback
164 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c programmable timer 19.2.3 pt2_cfg register the programmable timer configuration register (pt2_cfg) configures the psoc?s programmable timer. bit 2: clksel. this bit determines if the timer runs on the 32 khz clock or cpu clock. if the bit is set to 1'b1, the timer runs on the cpu clock, otherwise, the timer runs on the 32 khz clock. bit 1: one shot. this bit determines if the timer runs in one-shot mode or continuous mode. in one-shot mode the timer completes one full count cycle and terminates. upon termination, the start bit in this register is cleared. in con- tinuous mode, the timer reloads the count value each time upon completion of its count cycle and repeats. bit 0: start. this bit starts the timer counting from a full count. the full count is determined by the value loaded into the data registers. this bit is cleared when the timer is run- ning in one-shot mode upon comp letion of a full count cycle. for additional information, refer to the pt2_cfg register on page 225 . 19.2.4 ptx_data0 register the programmable timer data register 0 (pt0_data0, pt1_data0, pt2_data0) holds the lower 8 bits of the pro- grammable timer?s count value. bits 7 to 0: data[7:0]. this is the lower byte of a 16-bit timer. the upper byte is in the corresponding ptxdata1 register. for additional information, refer to the pt0_data0 register on page 223 , pt1_data0 register on page 223 and pt2_data0 register on page 223 . 19.2.5 ptx_data1 register the programmable timer data register 1 (pt0_data1, pt1_data1, pt2_data1) holds the 8 bits of the program- mable timer?s count value for the device bits 7 to 0: data[7:0]. this is the upper byte of a 16-bit timer. the lower byte is in the corresponding ptx_data0 register. for additional information, refer to the pt0_data1 register on page 222 , pt1_data1 register on page 222 , and pt2_data1 register on page 222 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,b6h pt2_cfg clksel one shot start rw : 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,b2h pt0_data0 data[7:0] rw : 00 0,b5h pt1_data0 data[7:0] rw : 00 0,b8h pt2_data0 data[7:0] rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,b1h pt0_data1 data[7:0] rw : 00 0,b4h pt1_data1 data[7:0] rw : 00 0,b7h pt2_data1 data[7:0] rw : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 165 20. full-speed usb this chapter explains the full-speed usb (universal serial bus) resource and its associated registers. for a quick reference of all psoc registers in address order, refer to the register reference chapter on page 187 . 20.1 architectural description the psoc usb system resource adheres to the usb 2.0 specification for full-speed devices operating at 12 mbps with one upstream port and one usb address. psoc usb consists of these components: serial interface engine (sie) block psoc memory arbiter (pma) block 512 bytes of dedicated sram a full-speed usb transceiver with internal regulator and two dedicated usb pins figure 20-1. usb block diagram at the psoc system level, the full-speed usb system resource interfaces to the rest of the psoc by way of the m8c's register access instructions and to the outside world by way of the two usb pins. the sie supports nine end- points including a bidirectional control endpoint (endpoint 0) and eight uni-directional data endpoints (endpoints 1 to 8). the uni-directional data endpoints are individually config- urable as either in or out. 20.2 application description the individual components and issues of the usb system are described in detail in the following sections. 20.2.1 usb sie the usb serial interface engine (sie) allows the psoc device to communicate with the usb host at full-speed data rates (12 mbps). the sie simplifies the interface to usb traffic by automatically handling the following usb process- ing tasks without firm ware intervention: translates the encoded received data and formats the data to be transmitted on the bus. generates and checks crcs. incoming packets failing checksum verification are ignored. checks addresses. ignores all transactions not addressed to the device. sends appropriate ack/nak/stall handshakes. identifies token type (setup, in, out) and sets the appropriate token bit once a valid token in received. identifies start-of-frame (sof) and saves the frame count. sends data to or retrieves data from the usb sram, by way of the psoc memory arbiter (pma). firmware is required to handle various parts of the usb interface. the sie issues interrupts after key usb events to direct firmware to appropriate tasks: fill and empty the usb data buffers in usb sram. enable pma channels appropriately. coordinate enumeration by decoding usb device requests. suspend and resume coordination. verify and select data toggle values. pma sie sie regs dm dp system bus usb xcvr sram [+] feedback
166 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c full-speed usb 20.2.2 usb sram the psoc usb system resource contains dedicated 512 bytes sram. this sram is identical to 2 sram pages used in the psoc core; however, it is not accessible by way of the m8c memory access instructions. the usb's dedicated sram may only be accessed by way of the pma registers. for more information on how to use the usb's dedicated sram, see the next section, psoc memory arbiter (pma). the usb sram contents are not directly affected by any reset, but must be treated as unknown after any por, wdr, and xres. 20.2.2.1 psoc memory arbiter the psoc memory arbiter (pma) is the interface between the usb's dedicated sram and the two blocks that access the sram: the m8c and the usb sie. the pma provides 16 channels to manage data with four endpoints/8 channels mapped to page 0 of usb dedicated sram and other four endpoints/8 channels mapped to page 1 of usb dedicated sram. all of the channel registers may be used by the m8c, but the eight non-control usb endpoints are each allo- cated to a specific set of pma channel registers. it is the responsibility of the firmware to ensure that the m8c is not accessing a set of channel registers that are in use by the usb sie. if the m8c wants to access the same data that an sie chan- nel is using, two channels must be configured to access the same sram address ranges. table 20-2 shows the map- ping between pma cha nnels and which blocks can use them. table 20-1. mode encoding for control and non-control endpoints mode encoding setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint. nak in/out 0001 accept nak nak nak in and out token. status out only 0010 accept stall check for control endpoint, stall in and ack zero byte out. stall in/out 0011 accept stall stall for control endpoint, stall in and out token. reserved 0100 ignore ignore ignore iso out 0101 ignore ignore always isochronous out. status in only 0110 accept tx 0 byte stall for control end point, stall out and send zero byte data for in token. iso in 0111 ignore tx count ignore isochronous in. nak out 1000 ignore ignore nak send nak handshake to out token. ack out (stall = 0) 1001 ignore ignore ack this mode is changed by the sie to mode 1000 on issuance of ack hand- shake to an out. ack out (stall = 1) 1001 ignore ignore stall stall the out transfer. reserved 1010 ignore ignore ignore ack out ? status in 1011 accept tx0 byte ack ack the out token or send zero byte data for in token. nak in 1100 ignore nak ignore send nak handshake for in token. ack in (stall = 0) 1101 ignore tx count ignore this mode is changed by the sie to mode 1100 after receiving ack hand- shake to an in data. ack in (stall = 1) 1101 ignore stall ignore stall the in transfer. reserved 1110 ignore ignore ignore ack in ? status out 1111 accept tx count c heck respond to in data or status out. table 20-2. pma channel assignments pma channel usb sie m8c channel registers (pmax_xx) 0 page 0 pma0_dr, pma0_ra, pma0_wa 1 ep1 page 0 pma1_dr, pma1_ra, pma1_wa 2 ep2 page 0 pma2_dr, pma2_ra, pma2_wa 3 ep3 page 0 pma3_dr, pma3_ra, pma3_wa 4 ep4 page 0 pma4_dr, pma4_ra, pma4_wa 5 page 0 pma5_dr, pma5_ra, pma5_wa 6 page 0 pma6_dr, pma6_ra, pma6_wa 7 page 0 pma7_dr, pma7_ra, pma7_wa 8 page 1 pma8_dr, pma8_ra, pma8_wa 9 ep5 page 1 pma9_dr, pma9_ra, pma9_wa 10 ep6 page 1 pma10_dr, pma10_ra, pma10_wa 11 ep7 page 1 pma11_dr, pma11_ra, pma11_wa 12 ep8 page 1 pma12_dr, pma12_ra, pma12_wa 13 page 1 pma13_dr, pma13_ra, pma13_wa 14 page 1 pma14_dr, pma14_ra, pma14_wa 15 page 1 pma15_dr, pma15_ra, pma15_wa [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 167 full-speed usb the pma's purpose is to manage the potentiall y conflicting sram access requests from the m8c and the usb sie. from a performance standpoint, the pma guarantees that a continuous stream of move instructions (see ahead), are serviced by the pma without de lay even while the usb sie is transferring data at its maximum rate in to or out of the dedicated usb sram. when servicing a request, the pma is in one of two address- ing modes. for m8c access the pma always uses post- increment addressing. after a read or write request is made to the channel's pmax_dr register, the pma automatically increments the pointer into sram. for a read access the next value is also automatically prefetched. for usb sie accesses, the pma uses an offset addressing mode. in this mode the channel's base address, as stored in the pmax_wa and pmax_ra registers, is added to the byte count value provided by the usb sie. a pma channel does not have a defined upper limit. it is the responsibility of the firmware to ensure that channels do not access memory outside of the range defined by the applica- tion. during sie writes to the usb sram, the maximum number of bytes written is limited to the count value in the respective endpoint's count registers. this value must be loaded by firmware before data is received. the rest of the descr iption of the pma is broken into two parts: the m8c interface and the usb sie interface, which are described as follows. pma to m8c interface the m8c accesses the pma, and thus the usb's dedicated sram, by way of a register interface. each pma channel has three registers associated with it as shown in ta b l e 2 0 - 2 on page 166 . only the following basic m8c register access instructions may be used with these registers. mov a, reg[expr] mov a, reg[x+expr] mov [expr], [expr] mov reg[expr], a mov reg[x+expr], a mov reg[expr], expr mov reg[x+expr], expr when the m8c uses a pma channel to write data into sram, follow these steps: 1. choose a pma channel that is not allocated to a usb endpoint, or choose a channel where the endpoint is inactive. 2. write the channel's pmax_wa register with the first address in sram that must be used by this channel. 3. write data to the channel's pmax_dr register. the pma logic automatically increments the pmax_wa address after each write. while these steps are executed by the m8c, the usb sie may be fully active on any other pma channel. the m8c may also service another channel and come back to the channel being serviced by the previous steps. to determine the next address that is used when data is written to the channel's pmax_dr r egister, the pmax_wa register may be read. when the m8c uses a pma channel to read data from sram, follow these steps: 1. choose a pma channel that is not allocated to a usb endpoint, or choose a channel where the endpoint is inactive. 2. write the channel's pmax_ra register with the first address in sram that must be read by this channel. 3. read data from the channel's pmax_dr register. the pma logic automatically increments the pmax_ra address after each read. when data is read from a pma channel the data is prefetched; therefore, the chann el must be pre-loaded prior to the first m8c read that expects to get actual data. this pre-loading is taken care of automatically when the pmax_ra register is written. this pre-loading mechanism is actually the only difference between the pmax_ra and pmax_wa registers. pma to usb sie interface the usb sie accesses the pma, and thus the dedicated usb sram, by way of a private interface and does not affect the psoc core address or data bus. the only area of contention that is not automatically arbitrated between the m8c, pma, and usb sie are the pmax_xx registers. when the usb sie is actively us ing a pma channel, the m8c must not attempt to access that ch annel's pma registers. if the m8c wants to access the same data as an active usb end- point, the m8c must use a pma channel separate from the pma channel that is permanently allocated to that endpoint. just as the m8c has two us es for pma channels, read or write, the usb sie has two uses for a pma channel. the usb sies use of a channel may be thought of as read or write; but, in usb terms the usb sies need to read data would be associated with an in transaction and the need to write data with an out transaction. [+] feedback
168 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c full-speed usb for a usb in transaction, the usb sie is reading data from the pma and sending the data to the usb host. the follow- ing steps must be used to set up a pma channel for a usb in transaction. these steps assume that the data has already been written by the m8c into the dedicated usb sram. 1. select the pma channel whose number matches the endpoint number that is handling the in transaction. 2. write the pma channel's pmax_ra register with the address of the first byte in sram that is used for the in transaction. 3. configure the usb endpoint registers with the proper byte count and enable the endpoint to send data when the in transaction occurs. because the pma prefetches data for m8c and usb sie reads, step two above is very important. this step not only sets the first address from which data is read by the usb sie; but, it also triggers a read operation on the dedicated usb sram and stores the result of that read in the pmax_dr ready for the usb sie to read. when the usb sie begins the in transaction for the endpoint, it uses its byte counter to tell the pma which byte is needed next. therefore, when the first byte of the transaction is read by the sie, the pma automatically fetches the next byte in preparation for the usb sies next byte request. for a usb out transaction, the usb sie is writing data to the pma that was received from the usb host. the following steps must be used to set up a pma channel for a usb out transaction. 1. select the pma channel whose number matches the endpoint number that is handling the out transaction. 2. write the pma channel's pmax_wa register with the address of the first byte in sram that is used for the out transaction. 3. configure the usb endpoint with the proper maximum receive byte count and enable the endpoint to receive the out transaction. as with the in transaction, the pma uses the byte counter from the sie as an offset to the value of the pmax_wa reg- ister. as the usb sie sends by tes to the pma, the counter is added to the base address and the data byte is written into the dedicated usb sram. should an error occur in the out transaction and the packet be resent by the usb host, the byte count is reset to zero and the pma writes the new data over top of the potentially corrupt data from the previous failed transaction. if the number of bytes received exceeds the count in the endpoint's count register, the extra bytes are not written into the usb sram, but the received byte count reported in the endpoint count registers includes the ignored bytes. 20.2.3 oscillator lock the psoc device can operate without using any external components, such as a crystal, and still achieve the clock accuracy required for full-speed usb. it does this by locking its internal oscillator to the incoming usb traffic. therefore, the initial accuracy of the osc illator may no t meet the required accuracy ( 0.25%), but it self-tunes to this preci- sion before the device needs to transmit usb data. this oscillator locki ng feature is dis abled by default and must be enabled by firmware. in usb systems, this feature must always be enabled unless the device is being used with an accurate external clock. the enablelock bit in the usb_cr1 register is used to turn on the locking feature. 20.2.4 transceiver the internal usb transceiver interfaces to the external usb bus to transmit and receive signals according to the usb 2.0 specification. in normal usb operation, the transceiver interfaces directly to the sie and no user interaction is needed after initialization. the usb enable bit in the usb_cr0 register must be set to enable the transceiver for usb operation. the i/o mode bit in usbio_cr1 must not be set during normal usb mode of operation. the trans- ceiver can also be used in non-usb modes, since the d+ and d- pins can be read and written through register control bits. this enables multi-purpose use of these pins (for exam- ple, in a system that supports both usb and ps/2 signaling). clearing the usb enable bit of usb_cr0 powers down the usb differential receiver and disables usb communication. for usb operation, the transceiver contains an internal 1.5 k pull up resistor on the d+ line. this resistor is isolated from the d+ pin at reset and is attached under firmware con- trol through the usbpuen bit in the usbio_cr1 register. after the d+ pull up resistor is connected to the d+ line, the system normally detects that as an attach and begins the usb enumeration process. no additional external pull up resistor must be added to the d+ line, since the transceiver signaling is optimized for use with the internal d+ pull up resistor. however, low value series resistors (24 ) must be added externally to meet the driving impedance requirement for full-speed usb. the transceiver also includes 5 k pull up resistors on both the d+ and d- pins for communication at ps/2 or similar sig- naling levels. these resistors are disconnected at reset and can be connected with the ps2puen bit in the usbio_cr1 register. the d+ and d- pins can also be driven individually high and low in both usb and non-usb modes. the state of those pins can be read in any mode. refer to the description of the usbio_cr0 and usbio_cr1 registers for more detail. 20.2.5 usb suspend loss of usb activity, while the usb vbus is still asserted, indicates that the device must enter usb suspend mode. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 169 full-speed usb (self-powered devices do not need to go into suspend mode.) this condition is detected by monitoring the bus activity bit in the usb_cr1 register. this bit must be polled periodically. if it reads high (bus activity present), it must be cleared by firmware. if no acti vity is detected for the desired time (for example, 3 ms), then the device must enter sus- pend mode. not all sleep modes preserve the usb configuration register states during sleep. the standby i2c-usb mode is the pre- ferred sleep mode for usb operation because the state of all usb registers is maintained during sleep. the other sleep modes do not preserve all of these registers to save sleep power. the usb regulator settings must not be changed when entering sleep state, since the regulator automatically enters a low power state for the given regulator mode (pass- through or regulating). 20.2.5.1 using standby i2c-usb sleep mode for usb suspend to enter standby i2c-usb mode, firmware powers down the desired functions, as it would to enter a standby i2c- usb mode sleep state as documented in 10.1.1 sleep con- trol implementation logic on page 74 , including writing the sleep bit of the cpu_scr0 regi ster. in this mode, usb configuration registers and data are preserved during sleep. 20.2.5.2 using standby or deep sleep modes for usb suspend the standby and deep sleep modes do not have hardware supported for usb suspend operation because not all usb registers are preserved in t hese modes. in usb parts, if there is a need to enter standby or deep sleep mode, then user firmware must save the non-retained registers to sram before entering into sleep and restore these registers once the device wakes up. the list of these registers is given below. some configuration registers retain their val- ues in all sleep modes: usb_cr0, usb_cr1, usbio_cr0, usbio_cr1, imo_tr, imo_tr1. in addition, the usb sram contents are preserved in all sleep modes. the usb registers that retain state in standby i2c-usb mode but not in other sleep modes are: the endpoint control registers (epx_crx), endpoint pma write address (pmax_wa)/read address (pmax_ra) registers, pma data registers (pmax_dr), endpoint count registers (epx_cntx), endpoint 0 data register (ep0_drx) and start of frame registers (usb_sofx). these registers are reset after the device comes out of sleep. (an alternative is to simply disconnect from the usb bus before going into one of these sleep modes, and then re- connect to re-initialize the usb system after waking up.) 20.2.5.3 wakeup from suspend the usb wake interrupt must be enabled to allow the device to exit the sleep state when there is activity on the usb bus. this interrupt can be enabled at any time since it only asserts when the device is in the sleep state. other inter- rupts may be optionally enabled, such as the sleep interrupt, gpio, i2c, to periodically wake the device while in usb suspend state. the usb wake interrupt can wake up the device from all the three sleep states (standby sleep, i2c- usb sleep and deep sleep). if d+ is low when the sleep bit is being set, the device briefly enters sleep state, and then exits sleep due to the usb wake interrupt. by carefully using a sleep timer interrupt, the device can wake periodically, monitor the environment, and return to sleep while maintaining a low average current that meets the usb suspend current specification. if the device needs to issue a resume signal to the usb sys- tem, firmware can write to the ten and td bits in the usbio_cr0 register to manually force a k state on the bus. using these bits produces signaling that meets the usb tim- ing specifications. when driving a resume, the j state (td=1) must be driven briefly before driving the k state (td=0). the steps are sum- marized as follows: 1. drive the j state (ten=1, td=1) for one instruction. 2. drive the resume, or k state (ten=1, td=0) for the proper time (1 ms to 15 ms). 3. stop driving the usb bus manually (ten=0). 20.2.6 regulator the transceiver contains a built-in regulator that can be used to power the transceiver from the usb bus voltage or other supply around 5v. the regulator supplies the proper levels for usb signals, which switch between 0v and 3.3v nominally. if the psoc device is operating with a vdd supply near 3.3v, then the regulator must be placed into a pass- through mode so that the vdd voltage is directly supplied to the transceiver, without regulation. the regenable bit (bit 0 in the usb_cr1 register) is used to pick between the regu- lating mode (5v supply) or the passthrough mode (3.3v sup- ply). at power up, the regulator is automatically held in pass- through mode, but the usb transceiver pins are tristated. [+] feedback
170 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c full-speed usb figure 20-2. transceiver and regulator block diagram voltage regulator 5v 3.3v s1 1.5k 5k ps2 pull up dp dm ten td pdn rd dpo rse0 dmo receivers transmitter [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 171 full-speed usb 20.3 register definitions the following registers are related to full-speed usb in the psoc device. for a complete table of the full-speed usb regis- ters, refer to the registers table summary table of the system resource registers on page 106 . register bits that are grayed out in this document are reserved bits and are not detailed in the register descriptions that follow. always write reserved bit s with a value of ?0?. 20.3.1 usb_sof0 register the usb start of frame registers (usb_sof0 and usb_sof1) provide access to the 11-bit sof frame num- ber. start of frame packets are sent from the host (for exam- ple, the pc) every 1 ms. for more information, see the universal serial bus specification, revision 2.0 . bits 7 to 0: frame number. the usb_sof0 register has the lower 8 bits [7:0] and the usb_sof1 register has the upper 3 bits [10:8] of the sof frame number. for additional information, refer to the usb_sof0 register on page 193 and the usb_sof1 register on page 194 . 20.3.2 usb_cr0 register the usb control register 0 (usb_cr0) is used to set the psoc?susb address and enable the usb system resource. all bits in this register are reset to zero when a usb bus reset interrupt occurs. note set the imo frequency to 24 mhz and enable the 48 mhz clock in the osc_cr2 register before usb is enabled. see imo_tr and cpu_scr1 registers for selecting imo frequency as 24 mhz. bit 7: usb enable. this bit enables the psoc device to respond to usb traffic. ?0? is usb disabled. the device does not respond to usb traffic. ?1? is usb enabled. bits 6 to 0: device address[6:0]. these bits specify the usb device address to which the sie responds. this address must be set by firmware and is specified by the usb host with a set addr ess command during usb enu- meration. this value must be programmed by firmware when assigned during enumeration. it is not set automati- cally by the hardware. for additional information, refer to the usb_cr0 register on page 195 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,31h usb_sof0 frame number[7:0] r : 00 0,32h usb_sof1 frame number[10:8] r : 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,33h usb_cr0 usb enable device address[6:0] rw : 00 [+] feedback
172 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c full-speed usb 20.3.3 usbio_cr0 register the usb i/o control register 0 (usbio_cr0) is used for manually transmitting on the usb d+ and d- pins, or read- ing the differential receiver. bit 7: ten. this is used to manually transmit on the d+ and d- pins. normally, this bit must be cleared to allow the inter- nal sie to drive the pins. the most common reason for man- ually transmitting is to force a resume state on the bus. ?0? is manual transmission off (tse0 and td have no effect). ?1? is manual transmission enabled (tse0 and td determine the state of the d+ and d- pins). bit 6: tse0. transmit single-ended zero. se0: both d+ and d- low. no effect if ten=0. ?0? is do not force se0. ?1? is force se0 on d+ and d-. bit 5: td. transmit a usb j or k state on the usb bus. no effect if ten=0 or tse0=1. ?0? forces usb k state (d+ is low, d- is high). ?1? forces usb j state (d+ is high, d- is low). bit 0: rd. this read only bit gives the state of the usb dif- ferential receiver. ?0? is d+ < d- or d+ = d- = 0. ?1? is d+ > d-. for additional information, refer to the usbio_cr0 register on page 196 . 20.3.4 usbio_cr1 register the usb i/o control register 1 (usbio_cr1) is used to manually read or write the d+ and d- pins, and to configure internal pull up resistors on those pins. bit 7: iomode. this bit allows the d+ and d- pins to be configured for either usb mode or bit banged modes. if this bit is set, the dmi and dpi bits are used to drive the d- and d+ pins. ?0? is usb mode. dr ive mode has no effect. ?1? is drive mode, dmi and dpi determine state of the d+ and d- pins. bit 6: drive mode. if the iomode bit is set, this bit config- ures the d- and d+ pins for ei ther cmos drive or open drain drive. if iomode is cleared, this bit has no effect. note that in open drain mode, 5 k pull up resistors can be connected internally with the ps2puen bit. ?0? is d+ and d- are in open drain mode. if the dpi or dmi bits are set high, the corre- sponding d+ or d- pad is high impedance. ?1? is d+ and d- are in cmos drive mode. d+ follows dpi and d- follows dmi. bit 5: dpi. this bit is used to drive the d+ pin if iomode=1. refer to the drive mode bit for drive state of pad. ?0? is drive d+ pad low. ?1? is drive d+ pad high (unless drive mode=0). bit 4: dmi. this bit is used to drive the d- pin if iomode=1. refer to the drive mode bit for drive state of pad. ?0? is drive d- pad low. ?1? is drive d- pad high (unless drive mode=0). bit 3: ps2puen. this bit controls the connection of the two internal 5 k pull up resistors to the d+ and d- pins. ?0? is no effect. ?1? is apply 5k pull ups between vdd and both d+ and d- pads, independent of the iomode and drive mode bits. bit 2: usbpuen. this bit controls the connection of the internal 1.5 k pull up resistor on the d+ pin. ?0? is no effect. ?1? is apply internal usb pull up resistor to d+ pad. bit 1: dpo. this read only bit gives the state of the d+ pin. bit 0: dmo. this read only bit gives the state of the d- pin. for additional information, refer to the usbio_cr1 register on page 197 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,34h usbio_cr0 ten tse0 td rd # : 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,35h usbio_cr1 iomode drive mode dpi dmi ps2puen usbpuen dpo dmo # : 03 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 173 full-speed usb 20.3.5 ep0_cr register the endpoint control register (ep0_cr) is used to config- ure endpoint 0. because both firmware and the sie are allowed to write to the endpoint 0 control and count registers, the sie pro- vides an interlocking mechanism to prevent accidental over- writing of data. when the sie writes to these registers they are locked and the processor cannot write to them until after reading the ep0_cr register. writing to this register clears the upper four bits regardless of the value written. note the register lock is removed when the following m8c instructions are used to write the ep0_cr register as these instructions generate a read (ior_) signal, which causes the lock to be removed even without the firmware actually reading the ep0_cr register. mov reg[expr], expr mov reg[x+expr], expr bit 7: setup received. when set, this bit indicates a valid setup packet was received and ack?ed. this bit is forced high from the start of the data packet phase of the setup transaction, until the start of the ack packet returned by the sie. the cpu is prevented from clearing this bit during this interval. after this interval, the bit remains set until cleared by firmware. while this bit is set to '1', the cpu cannot write to the ep0_drx registers. this prevents firmware from overwriting an incoming setup transaction before firmware has a chance to read the setup data. this bit is cleared by any non-locked writes to the register. bit 6: in received. when set, this bit indicates a valid in packet has been received. this bit is updated to '1' after the host acknowledges an in data packet. when clear, this bit indicates either no in has been received or that the host did not acknowledge the in data by sending an ack hand- shake. it is cleared by any non-locked writes to the register. bit 5: out received. when set, this bit indicates a valid out packet has been received and ack?ed. this bit is updated to '1' after the last received packet in an out trans- action. when clear, this bit indicates no out has been received. it is cleared by any non-locked writes to the regis- ter. bit 4: ack?ed transaction. this bit is set whenever the sie engages in a transaction to the register's endpoint that completes with an ack packet. this bit is cleared by any non-locked writes to the register. bits 3 to 0: mode[3:0]. the mode bits control how the usb sie responds to traffic and how the usb sie changes the mode of that endpoint as a result of host packets to the end- point. for additional information, refer to the ep0_cr register on page 198 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,36h ep0_cr setup received in received out received ack?ed transaction mode[3:0] # : 00 [+] feedback
174 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c full-speed usb 20.3.6 ep0_cnt register the endpoint 0 count register (ep0_cnt) is used to con- figure endpoint 0. whenever the count updates fr om a setup or out transac- tion, this register locks and cannot be written by the cpu. reading the ep0_cr register unlocks this register. this pre- vents firmware from overwriting a status update on incoming setup or out transactions, before firmware has a chance to read the data. bit 7: data toggle. this bit selects the data packet's toggle state. for in transactions, firmware must set this bit. for out or setup transactions, the sie hardware sets this bit to the state of the received data toggle bit. ?0? is data0. ?1? is data1. bit 6: data valid. this bit indicates whether there were errors in out or setup transactions. it is cleared to '0' if crc, bit stuff, or pid errors have occurred. this bit does not update for some endpoint mode settings. this bit may be cleared by writing a zero to it when the register is not locked. ?0? is error in data re ceived. ?1? is no error. bits 3 to 0: byte count[3:0]. these bits indicate the num- ber of data bytes in a transaction. for in transactions, firm- ware loads the count with the number of bytes to be transmitted to the host from the endpoint fifo. valid values are 0 to 8. for out or setup transactions, the count is updated by hardware to the number of data bytes received, plus two for the crc bytes. valid values are 2 to 10. for additional information, refer to the ep0_cnt register on page 199 . 20.3.7 ep0_drx register the endpoint 0 data register (ep0_drx) is used to read and write data to the usb control endpoint. the ep0_drx registers have a hardware-locking feature that prevents the cpu write when setup is active. the regis- ters are locked as soon as the setup token is decoded and remain locked throughout the setup transaction and until the ep0_cr register has been read. th is is to prevent overwrit- ing new setup data before firmware knows it has arrived. all other endpoint data buffers do not have this locking fea- ture. bits 7 to 0: data byte[7:0]. these registers are shared for both transmit and receive. the count in the ep0_cnt regis- ter determines the number of bytes received or to be trans- ferred. for additional information, refer to the ep0_drx register on page 200 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,37h ep0_cnt data toggle data valid byte count[3:0] # : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,38h ep0_dr0 data byte[7:0] rw : 00 0,39h ep0_dr1 data byte[7:0] rw : 00 0,3ah ep0_dr2 data byte[7:0] rw : 00 0,3bh ep0_dr3 data byte[7:0] rw : 00 0,3ch ep0_dr4 data byte[7:0] rw : 00 0,3dh ep0_dr5 data byte[7:0] rw : 00 0,3eh ep0_dr6 data byte[7:0] rw : 00 0,3fh ep0_dr7 data byte[7:0] rw : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 175 full-speed usb 20.3.8 epx_cnt1 register the endpoint count register 1 (epx_cnt1) sets or reports the number of bytes in a usb data transfer to the non-con- trol endpoints. bit 7 to 0: data count. these bits are the eight lsb of a 9-bit counter. the msb is the count msb bit of the epx_cnt0 register. the 9-bit count indicates the number of data bytes in a transaction. for in transactions, firmware loads the count with the number of data bytes to be transmit- ted to the host. valid values are 0 to 256. the 9-bit count also sets the limit for the number of bytes that are received for an out transaction. before an out transaction is received for an endpoint, this count value must be set to the maximum number of data bytes to receive. if this count value is set to a value greater than the number of bytes (data + crc) received, both the data from the usb packet and the two-byte crc are written to the usb's dedicated sram. if the number of data bytes received is exactly the same as the 9-bit count, then only the data is updated into the usb sram and the crc is discarded but the out transaction is completed according to the mode bits of the epx control register. if the number of data bytes received is more than the 9-bit count, then the out transaction is ignored. after the out transaction is co mplete, the full 9-bit count is updated by the sie to the actual number of data bytes received by the sie plus two for the packet's crc. valid val- ues are 2 to 258. to get the actual number of bytes received, firmware must decrement the 9-bit count by two. for additional information, refer to the epx_cnt1 register on page 202 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,41h ep1_cnt1 data count[7:0] rw : 00 0,43h ep2_cnt1 data count[7:0] rw : 00 0,45h ep3_cnt1 data count[7:0] rw : 00 0,47h ep4_cnt1 data count[7:0] rw : 00 0,49h ep5_cnt1 data count[7:0] rw : 00 0,4bh ep6_cnt1 data count[7:0] rw : 00 0,4dh ep7_cnt1 data count[7:0] rw : 00 0,4fh ep8_cnt1 data count[7:0] rw : 00 [+] feedback
176 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c full-speed usb 20.3.9 epx_cnt0 register the endpoint count register 0 (epx_cnt0) is used for con- figuring endpoints 1 through 8. bit 7: data toggle. this bit selects the data packet's toggle state. for in transactions, firmware must set this bit to the expected state. for out transactions, the hardware sets this bit to the state of the received data toggle bit. ?0? is data0. ?1? is data1. bit 6: data valid. this bit is used for out transactions only and is read only. it is cleared to '0' if crc, bit stuffing errors, or pid errors occur. this bit does not update for some end- point mode settings. ?0? is error in data received. ?1? is no error. bit 0: count msb. this bit is the one msb of a 9-bit counter. the lsb are the data count[7:0] bits of the epx_cnt1 register. refer to the epx_cnt1 register for more information. for additional information, refer to the epx_cnt0 register on page 201 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,40h ep1_cnt0 data toggle data valid count msb # : 0 0,42h ep2_cnt0 data toggle data valid count msb # : 0 0,44h ep3_cnt0 data toggle data valid count msb # : 0 0,46h ep4_cnt0 data toggle data valid count msb # : 0 0,48h ep5_cnt0 data toggle data valid count msb # : 0 0,4ah ep6_cnt0 data toggle data valid count msb # : 0 0,4ch ep7_cnt0 data toggle data valid count msb # : 0 0,4eh ep8_cnt0 data toggle data valid count msb # : 0 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 177 full-speed usb 20.3.10 epx_cr0 register the endpoint control register 0 (epx_cr0) is used for sta- tus and configuration of the non-control endpoints 1 to 8. bit 7: stall. when this bit is set, the sie stalls an out packet if the mode bits are set to ack-out. the sie stalls an in packet if the mode bits are set to ack-in. this bit must be cleared for all other modes. ?0? is do not issue a stall. ?1? is stall an out packet if mode bits are set to ack- out, or stall an in packet if mode bits are set to ack-in. bit 5: nak int enable. when set, this bit causes an end- point interrupt to be generated even when a transfer com- pletes with a nak. ?0? is do not issue an interrupt after completing the transaction by sending nak. ?1? is interrupt after transaction is complete by sending nak. bit 4: ack?ed transaction. the ack'ed transaction bit is set whenever the sie engages in a transaction to the regis- ter's endpoint that completes with an ack packet. this bit is cleared by any writes to the register. ?0? is no ack'ed trans- actions since bit was last cleared. ?1? indicates a transaction ended with an ack. bits 3 to 0: mode[3:0]. the mode controls how the usb sie responds to traffic and how the usb sie changes the mode of that endpoint as a result of host packets to the end- point. refer to ?mode encoding for control and non-control endpoints? on page 166 . for additional informat ion, refer to the epx_cr0 register on page 265 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,54h ep1_cr0 stall nak_int_en ack?ed tx mode[3:0] # : 00 1,55h ep2_cr0 stall nak_int_en ack?ed tx mode[3:0] # : 00 1,56h ep3_cr0 stall nak_int_en ack?ed tx mode[3:0] # : 00 1,57h ep4_cr0 stall nak_int_en ack?ed tx mode[3:0] # : 00 1,58h ep5_cr0 stall nak_int_en ack?ed tx mode[3:0] # : 00 1,59h ep6_cr0 stall nak_int_en ack?ed tx mode[3:0] # : 00 1,5ah ep7_cr0 stall nak_int_en ack?ed tx mode[3:0] # : 00 1,5bh ep8_cr0 stall nak_int_en ack?ed tx mode[3:0] # : 00 [+] feedback
178 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c full-speed usb 20.3.11 pmax_wa register the psoc memory arbiter write address register (pmax_wa) is used to set the beginning sram address for the pma channel. a pmax_wa register address uses the same physical register as the pmax_ra register address. therefore, when the read address is changed, the write address is also changed and the pmax_ra and pmax_wa registers always return the same value when read. bits 7 to 0: address[7:0]. the value returned when this register is read depends on whether the pma channel is being used by the usb sie or by the m8c. in the usb case, this register always returns the beginning sram address for the pma channel. in the m8c ca se, this register always returns the next sram address that is used by the pma channel, if a byte is written to the channel's data register (pmax_dr) by the m8c. for additional information, refer to the pmax_wa register on page 263 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,34h pma0_wa write address[7:0] rw : 00 1,35h pma1_wa write address[7:0] rw : 00 1,36h pma2_wa write address[7:0] rw : 00 1,37h pma3_wa write address[7:0] rw : 00 1,38h pma4_wa write address[7:0] rw : 00 1,39h pma5_wa write address[7:0] rw : 00 1,3ah pma6_wa write address[7:0] rw : 00 1,3bh pma7_wa write address[7:0] rw : 00 1,44h pma8_wa write address[7:0] rw : 00 1,45h pma9_wa write address[7:0] rw : 00 1,46h pma10_wa write address[7:0] rw : 00 1,47h pma11_wa write address[7:0] rw : 00 1,48h pma12_wa write address[7:0] rw : 00 1,49h pma13_wa write address[7:0] rw : 00 1,4ah pma14_wa write address[7:0] rw : 00 1,4bh pma15_wa write address[7:0] rw : 00 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 179 full-speed usb 20.3.12 pmax_dr register the psoc memory arbiter data register (pmax_dr) is used to read and write to a particular pma channel by either the usb sie or the m8c. note that a pma channel may not be used simultaneously by both the usb sie and the m8c. bits 7 to 0: data byte[7:0]. when the m8c writes to this register, the pma registers th e byte and then stores the value at the address in sr am indicated by the pmax_wa register. after the value has been wr itten to sram, the pmax_wa register is automatically incremented. when the usb sie writes to this register, the pma registers the byte and then stores the value in sram using the sum of the value of the pmax_wa register and the usb sies received byte count. when the m8c reads this register, a pre-loaded value is returned and the pmax_ra valu e is automatically incre- mented. the new pmax_ra value is used to fetch the next value from the sram, to be ready for the next read from the chan- nel's pmax_dr register. when the usb sie reads the pmax_dr register, it also receives a pre-loaded value, which triggers the pma logic to fetch the next value in sram to be ready for the usb sies next read request. in all read cases, the initial pre-load of the first address of the channel is triggered by writing the first address of the chan- nel to the channel's pmax_ra register. therefore, the pmax_ra register must be wr itten after data has been stored for the channel. for additional information, refer to the pmax_dr register on page 203 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 0,58h pma0_dr data byte[7:0] rw : 00 0,59h pma1_dr data byte[7:0] rw : 00 0,5ah pma2_dr data byte[7:0] rw : 00 0,5bh pma3_dr data byte[7:0] rw : 00 0,5ch pma4_dr data byte[7:0] rw : 00 0,5dh pma5_dr data byte[7:0] rw : 00 0,5eh pma6_dr data byte[7:0] rw : 00 0,5fh pma7_dr data byte[7:0] rw : 00 0,64h pma8_dr data byte[7:0] rw : 00 0,65h pma9_dr data byte[7:0] rw : 00 0,66h pma10_dr data byte[7:0] rw : 00 0,67h pma11_dr data byte[7:0] rw : 00 0,68h pma12_dr data byte[7:0] rw : 00 0,69h pma13_dr data byte[7:0] rw : 00 0,6ah pma14_dr data byte[7:0] rw : 00 0,6bh pma15_dr data byte[7:0] rw : 00 [+] feedback
180 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c full-speed usb 20.3.13 pmax_ra register the psoc memory arbiter read address register (pmax_ra) is used to set the beginning address for the pma channel. a pmax_ra register address uses the same physical register as the pmax_wa register address. there- fore, when the read address is changed, the write address is also changed and the pmax _wa and pmax_ra registers always return the same value when read. when a pmax_ra register is written, the address is stored and the value of the corresponding sram address is loaded into the channel's pmax_dr. t herefore, this register must only be written after valid data has been stored in sram for the channel. bits 7 to 0: address[7:0]. the value returned when this register is read depends on whether the pma channel is being used by the usb sie or by the m8c. in the usb sie case, this register always returns the beginning sram address for the pma channel. in the m8c case, this register always returns the next sram address that is used by the pma channel, if a byte is read from the channel's data regis- ter (pmax_dr) by the m8c. for additional information, refer to the pmax_ra register on page 264 . 20.3.14 usb_cr1 register the usb control register 1 (usb_cr1) is used to config- ure the internal regulator and the oscillator tuning capability. bit 2: busactivity. the busactivity bit is a "sticky" bit that detects any non-idle usb event that has occurred on the usb bus. after set to high by the sie to indicate the bus activity, this bit retains its logical high value until firmware clears it. writing a '0' to this bit clears it; writing a '1' pre- serves its value. ?0? is no activity. '1' is non-idle activity (d+ = low) was detected since the last time the bit was cleared. bit 1: enablelock. set this bit to turn on the automatic fre- quency locking of the internal oscillator to usb traffic. unless an external clock is being provided, this bit must remain set for proper usb operation. ?0? is locking disabled. '1' is locking enabled. bit 0: regenable. this bit controls the operation of the internal usb regulator. for applications with device supply voltages in the 5v range, set this bit high to enable the inter- nal regulator. for device supply voltages in the 3.3v range, clear this bit to connect the transceiver directly to the supply. ?0? is passthrough mode. use for vdd = 3.3v range. '1' is regulating mode. use for vdd = 5v range. for additional information, refer to the usb_cr1 register on page 262 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,3ch pma0_ra read address[7:0] rw : 00 1,3dh pma1_ra read address[7:0] rw : 00 1,3eh pma2_ra read address[7:0] rw : 00 1,3fh pma3_ra read address[7:0] rw : 00 1,40h pma4_ra read address[7:0] rw : 00 1,41h pma5_ra read address[7:0] rw : 00 1,42h pma6_ra read address[7:0] rw : 00 1,43h pma7_ra read address[7:0] rw : 00 1,4ch pma8_ra read address[7:0] rw : 00 1,4dh pma9_ra read address[7:0] rw : 00 1,4eh pma10_ra read address[7:0] rw : 00 1,4fh pma11_ra read address[7:0] rw : 00 1,50h pma12_ra read address[7:0] rw : 00 1,51h pma13_ra read address[7:0] rw : 00 1,52h pma14_ra read address[7:0] rw : 00 1,53h pma15_ra read address[7:0] rw : 00 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,30h usb_cr1 busactivity enablelock regenable # : 0 [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 181 full-speed usb 20.3.15 imo_tr1 register internal register ? the internal main oscillator trim register 1 (imo_tr1) fine tunes the imo frequency. for information on the other imo trim register (imo_tr) see the internal main oscillator chapter or refer to the imo_tr1 register on page 286 in the register details chapter. bits 2 to 0: fine trim[2:0]. these bits provide a fine tuning capability to the imo trim. these three bits are the three lsb of the imo trim with the imo_tr register supplying the eight msb. for additional information, refer to the imo_tr1 register on page 286 . 20.3.16 related registers usb_misc_cr register on page 112 . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 access 1,fah imo_tr1 fine trim[2:0] rw : 00 [+] feedback
182 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c full-speed usb [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 183 section e: registers the registers section discusses the registers of the psoc device . it lists all the registers in mapping tables, in address orde r. for easy reference, each register is linked to the page of a detailed description located in the next chapter. this section encompasses the following chapter: register reference chapter on page 187 . register general conventions the register conventions specific to this section and the register reference chapter are listed in the following table: register mapping tables the psoc device has a total register address space of 512 bytes. the register space is also referred to as i/o space and is broken into two parts: bank 0 (user space) and bank 1 (configuration space). the xio bit in the flag register (cpu_f) determines which bank the user is currently in. when the xio bit is set, the user is said to be in the ?extended? address space or the ?configuration? registers. refer to the individual psoc device data sheets for device- specific register mapping information. register conventions convention description empty, grayed-out table cell illustrates a reserved bit or group of bits. ?x? before the comma in an address indicates the register exists in register bank 1 and register bank 2. ?x? in a register name indicates that there are multiple instances/address ranges of the same register. r read register or bit(s). w write register or bit(s). o only a read/write register or bit(s). l logical register or bit(s). c clearable register or bit(s). # access is bit specific. [+] feedback
184 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section e: registers register map bank 0 table: user space name addr (0,hex) access page name addr (0,hex) access page name addr (0,hex) access page name addr (0,hex) access page prt0dr 00 rw 188 ep1_cnt0 40 # 201 80 c0 prt0ie 01 rw 189 ep1_cnt1 41 rw 202 81 c1 02 ep2_cnt0 42 # 201 82 c2 03 ep2_cnt1 43 rw 202 83 c3 prt1dr 04 rw 188 ep3_cnt0 44 # 201 84 c4 prt1ie 05 rw 189 ep3_cnt1 45 rw 202 85 c5 06 ep4_cnt0 46 # 201 86 c6 07 ep4_cnt1 47 rw 202 87 c7 prt2dr 08 rw 188 ep5_cnt0 48 # 201 88 i2c_xcfg c8 rw 226 prt2ie 09 rw 189 ep5_cnt1 49 rw 202 89 i2c_xstat c9 r 227 0a ep6_cnt0 4a # 201 8a i2c_addr ca rw 228 0b ep6_cnt1 4b rw 202 8b i2c_bp cb r 229 prt3dr 0c rw 188 ep7_cnt0 4c # 201 8c i2c_cp cc r 230 prt3ie 0d rw 189 ep7_cnt1 4d rw 202 8d cpu_bp cd rw 231 0e ep8_cnt0 4e # 201 8e cpu_cp ce r 232 0f ep8_cnt1 4f rw 202 8f i2c_buf cf rw 233 prt4dr 10 rw 188 50 90 cur_pp d0 rw 234 prt4ie 11 rw 189 51 91 stk_pp d1 rw 235 12 52 92 d2 13 53 93 idx_pp d3 rw 236 14 54 94 mvr_pp d4 rw 237 15 55 95 mvw_pp d5 rw 238 16 56 96 i2c_cfg d6 rw 239 17 57 97 i2c_scr d7 # 240 18 pma0_dr 58 rw 203 98 i2c_dr d8 rw 241 19 pma1_dr 59 rw 203 99 d9 1a pma2_dr 5a rw 203 9a int_clr0 da rw 242 1b pma_dr 5b rw 203 9b int_clr1 db rw 244 1c pma4_dr 5c rw 203 9c int_clr2 dc rw 246 1d pma5_dr 5d rw 203 9d dd 1e pma6_dr 5e rw 203 9e int_msk2 de rw 248 1f pma7_dr 5f rw 203 9f int_msk1 df rw 249 20 60 cs_cr0 a0 rw 211 int_msk0 e0 rw 250 21 amux_cfg 61 rw 204 cs_cr1 a1 rw 212 int_sw_en e1 rw 251 22 62 cs_cr2 a2 rw 213 int_vc e2 rc 252 23 63 cs_cr3 a3 rw 214 res_wdt e3 w 253 24 pma8_dr 64 rw 203 cs_cntl a4 rw 215 e4 25 pma9_dr 65 rw 203 cs_cnth a5 rw 216 e5 26 pma10_dr 66 rw 203 cs_stat a6 # 217 e6 27 pma11_dr 67 rw 203 cs_timer a7 rw 218 e7 28 pma12_dr 68 rw 203 cs_slew a8 rw 219 e8 spi_txr 29 w 190 pma13_dr 69 rw 203 prs_cr a9 rw 220 e9 spi_rxr 2a r 191 pma14_dr 6a rw 203 aa ea spi_cr 2b # 192 pma15_dr 6b rw 203 ab eb 2c tmp_dr0 6c rw 266 ac ec 2d tmp_dr1 6d rw 266 ad ed 2e tmp_dr2 6e rw 266 ae ee 2f tmp_dr3 6f rw 266 af ef 30 70 pt0_cfg b0 rw 221 f0 usb_sof0 31 r 193 71 pt0_data1 b1 rw 223 f1 usb_sof1 32 r 194 72 pt0_data0 b2 rw 223 f2 usb_cr0 33 rw 195 73 pt1_cfg b3 rw 224 f3 usbio_cr0 34 # 196 74 pt1_data1 b4 rw 223 f4 usbio_cr1 35 # 197 75 pt1_data0 b5 rw 223 f5 ep0_cr 36 # 198 76 pt2_cfg b6 rw 225 f6 ep0_cnt0 37 # 199 77 pt2_data1 b7 rw 223 cpu_f f7 rl 254 ep0_dr0 38 rw 200 cmp_rdc 78 # 205 pt2_data0 b8 rw 223 f8 ep0_dr1 39 rw 200 cmp_mux 79 rw 206 b9 f9 ep0_dr2 3a rw 200 cmp_cr0 7a rw 207 ba fa ep0_dr3 3b rw 200 cmp_cr1 7b rw 208 bb fb ep0_dr4 3c rw 200 cmp_lut 7c rw 210 bc fc ep0_dr5 3d rw 200 7d bd idac_d fd rw 256 ep0_dr6 3e rw 200 7e be cpu_scr1 fe # 257 ep0_dr7 3f rw 200 7f bf cpu_scr0 ff # 258 gray fields are reserved. # access is bit specific. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 185 section e: registers register map bank 1 tabl e: configuration space name addr (1,hex) access page name addr (1,hex) access page name addr (1,hex) access page name addr (1,hex) access page prt0dm0 00 rw 259 pma4_ra 40 rw 264 80 c0 prt0dm1 01 rw 260 pma5_ra 41 rw 264 81 c1 02 pma6_ra 42 rw 264 82 c2 03 pma7_ra 43 rw 264 83 c3 prt1dm0 04 rw 259 pma8_wa 44 rw 263 84 c4 prt1dm1 05 rw 260 pma9_wa 45 rw 263 85 c5 06 pma10_wa 46 rw 263 86 c6 07 pma11_wa 47 rw 263 87 c7 prt2dm0 08 rw 259 pma12_wa 48 rw 263 88 c8 prt2dm1 09 rw 260 pma13_wa 49 rw 263 89 c9 0a pma14_wa 4a rw 263 8a ca 0b pma15_wa 4b rw 263 8b cb prt3dm0 0c rw 259 pma8_ra 4c rw 264 8c cc prt3dm1 0d rw 260 pma9_ra 4d rw 264 8d cd 0e pma10_ra 4e rw 264 8e ce 0f pma11_ra 4f rw 264 8f cf prt4dmo 10 rw 260 pma12_ra 50 rw 264 90 d0 prt4dm1 11 rw 260 pma13_ra 51 rw 264 91 out_p0 d1 rw 268 12 pma14_ra 52 rw 264 92 eco_enbus d2 rw 269 13 pma15_ra 53 rw 264 93 eco_trim d3 rw 270 14 ep1_cr0 54 # 265 94 d4 15 ep2_cr0 55 # 265 95 d5 16 ep3_cr0 56 # 265 96 d6 17 ep4_cr0 57 # 265 97 d7 18 ep5_cr0 58 # 265 98 mux_cr0 d8 rw 271 19 ep6_cro 59 # 265 99 mux_cr1 d9 rw 271 1a ep7_cr0 5a # 265 9a mux_cr2 da rw 271 1b ep8_cr0 5b # 265 9b mux_cr3 db rw 271 1c 5c 9c io_cfg1 dc rw 272 1d 5d 9d out_p1 dd rw 273 1e 5e 9e io_cfg2 de rw 275 1f 5f 9f mux_cr4 df rw 271 20 60 a0 osc_cr0 e0 rw 276 21 61 a1 eco_cfg e1 # 277 22 62 a2 osc_cr2 e2 rw 278 23 63 a3 vlt_cr e3 rw 279 24 64 a4 vlt_cmp e4 r 280 25 65 a5 e5 26 66 a6 e6 27 67 a7 e7 28 68 a8 imo_tr e8 w 281 spi_cfg 29 rw 261 69 a9 ilo_tr e9 w 282 2a 6a aa ea 2b 6b ab slp_cfg eb rw 283 2c tmp_dr0 6c rw 266 ac slp_cfg2 ec rw 284 2d tmp_dr1 6d rw 266 ad slp_cfg3 ed rw 285 2e tmp_dr2 6e rw 266 ae ee 2f tmp_dr3 6f rw 266 af ef usb_cr1 30 # 262 70 b0 f0 31 71 b1 f1 32 72 b2 f2 33 73 b3 f3 pma0_wa 34 rw 263 74 b4 f4 pma1_wa 35 rw 263 75 b5 f5 pma2_wa 36 rw 263 76 b6 f6 pma3_wa 37 rw 263 77 b7 cpu_f f7 rl 254 pma4_wa 38 rw 263 78 b8 f8 pma5_wa 39 rw 263 79 b9 f9 pma6_wa 3a rw 263 7a ba imo_tr1 fa rw 286 pma7_wa 3b rw 263 7b bb fb pma0_ra 3c rw 264 7c bc fc pma1_ra 3d rw 264 7d usb_misc_cr bd rw 267 fd pma2_ra 3e rw 264 7e be fe pma3_ra 3f rw 264 7f bf ff gray fields are reserved # access is bit specific. [+] feedback
186 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c section e: registers [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 187 21. register reference this chapter is a reference for all the psoc device registers in address order, fo r bank 0 and bank 1. the most detailed descriptions of the psoc registers are in the register definitions section of each chapter. the registers that are in both bank s are incorporated with the bank 0 registers, designated with an ?x?, rather than a ?0? preceding the comma in the address. bank 0 registers are listed first and begin on page 188 . bank 1 registers are listed second and begin on page 259 . a condensed view of all the registers is shown in the register mapping tables starting on page 183 . 21.1 maneuvering around the registers for ease-of-use, this chapter has been formatted so that ther e is one register per page, although some registers use two pages. on each page, from top to bottom, there are four sections: 1. register name and address (from lowest to highest). 2. register table showing the bit organization, with reserved bits grayed out. 3. written description of register specifics or links to additional register information. 4. detailed register bit descriptions. use the register tables, in addition to the detailed register bit descriptions, to determine which bits are reserved. reserved bits are grayed table cells and are not described in the bit descripti on section. reserved bits must always be written with a value of ?0?. for all registers, an ?x? before the comma in the address field indicates that the register can be accessed or written to no matter what bank is used. for example, the m8c flag register?s (cpu_f) address is ?x,f7h? meaning it is located in bank 0 and bank 1 at f7h. 21.2 register conventions the following table lists the register conventions that are specific to this chapter. register conventions convention example description ?x? in a register name prtxie multiple instanc es/address ranges of the same register. r r : 00 read register or bit(s). w w : 00 write register or bit(s). o ro : 00 only a read/write register or bit(s). l rl : 00 logical register or bit(s). c rc : 00 clearable register or bit(s). 00 rw : 00 reset value is 0x00 or 00h. xx rw : xx register is not reset. 0, 0,04h register is in bank 0. 1, 1,23h register is in bank 1. x, x,f7h register exists in register bank 0 and register bank 1. empty, grayed-out table cell reserved bit or group of bits, unless otherwise stated. [+] feedback
188 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c prtxdr 0,00h 21.3 bank 0 registers the following registers are all in bank 0 and are listed in address order. an ?x? before the comma in the register?s address in di- cates that the register can be accessed in bank 0 and bank 1, independent of the xio bit in the cpu_f register. registers that are in both bank 0 and bank 1 are listed in address order in bank 0. for example, the rdixlt1 register has an address of x,b4h and is listed only in bank 0 but is accessed in both bank 0 and bank 1. 21.3.1 prtxdr port data registers these registers allow for write or read access, or the current logical equivalent, of pin voltage. the upper nibble of the prt4dr register returns the last data bus value when read. you need to mask it off before using this information. for additional information, refer to the register definitions on page 59 in the gpio chapter. 7:0 data[7:0] write value to port or read value from port. reads re turn the state of the pin, not the value in the prtxdr register. individual register names and addresses: 0,00h prt0dr : 0,00h prt1dr : 0,04h prt2dr : 0,08h prt3dr : 0,0ch prt4dr : 0,10h 7 6 5 4 3 2 1 0 access : por rw : 00 bit name data[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 189 prtxie 0,01h 21.3.2 prtxie port interrupt enable registers these registers enable or disable inte rrupts from individual gpio pins. the upper nibble of the prt4ie register returns the last data bus value when read and must be masked off before using this information. for additional information, refer to the register definitions on page 59 in the gpio chapter. 7:0 interrupt enables[7:0] these bits enable the corresponding port pin interr upt. only four lsb are used since this port has four pins. 0 port pin interrupt disabled for the corresponding pin. 1 port pin interrupt enabled for the corresponding pin. interrupt mode is determined by the ioint bit in the io_cfg1 register. individual register names and addresses: 0,01h prt0ie : 0,01h prt1ie : 0,05h prt2ie : 0,09h prt3ie : 0,0dh prt4ie : 0,11h 7 6 5 4 3 2 1 0 access : por rw : 00 bit name interrupt enables[7:0] bit name description [+] feedback
190 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi_txr 0,29h 21.3.3 spi_txr spi transmit data register this register is the spi?s transmit data register. for additional information, refer to the register definitions on page 147 in the spi chapter. 7:0 data[7:0] data for selected function. individual register names and addresses: 0,29h spi_txr : 0,29h 7 6 5 4 3 2 1 0 access : por w : 00 bit name data[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 191 spi_rxr 0,2ah 21.3.4 spi_rxr spi receive data register this register is the spi?s receive data register. for additional information, refer to the register definitions on page 147 in the spi chapter. 7:0 data[7:0] data for selected function. individual register names and addresses: 0,2ah spi_rxr : 0,2ah 7 6 5 4 3 2 1 0 access : por r : 00 bit name data[7:0] bit name description [+] feedback
192 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c spi_cr 0,2bh 21.3.5 spi_cr spi control register this register is the spi control register. the lsb first, clock phase, and clock polarity bits are conf iguration bits. do not change them once the block is enabled. these bits can be set at the same time that the block is enabled. for additional information, refer to the register definitions on page 147 in the spi chapter. 7lsb first do not change this bit during an spi transfer. 0 data is shifted out msb first. 1 data is shifted out lsb first. 6overrun 0 no overrun has occurred. 1 overrun has occurred. indicates that a new byte is received and loaded into the rx buffer before the previous one is read. it is clear ed on a read of this (cr0) register. 5 spi complete 0 indicates that a byte may still be in the proce ss of shifting out, or no transmission is active. 1 indicates that a byte is shifted out and all as sociated clocks are generated. it is cleared on a read of this (cr0) register. optional interrupt. 4 tx reg empty reset state and the state when the block is disabled is ?1?. 0 indicates that a byte is currently buffered in the tx register. 1 indicates that a byte is written to the tx r egister and cleared on write of the tx buffer (dr1) register. this is the default interrupt. this st atus is initially asserted on block enable; how- ever, the tx reg empty interrupt occurs only after the first data byte is written and trans- ferred into the shifter. 3rx reg full 0 rx register is empty. 1 a byte is received and loaded into the rx regi ster. it is cleared on a read of the rx buffer (dr2) register. 2 clock phase 0 data is latched on the leading clock edge. data changes on the trailing edge (modes 0, 1). 1 data changes on the leading clock edge. data is latched on the trailing edge (modes 2, 3). 1 clock polarity 0 non-inverted, clock idles low (modes 0, 2). 1 inverted, clock idles high (modes 1, 3). 0enable 0 spi function is not enabled. 1 spi function is enabled. individual register names and addresses: 0,2bh spi_cr : 0,2bh 7 6 5 4 3 2 1 0 access : por rw : 0 r : 0 r : 0 r : 1 r : 0 rw : 0 rw : 0 rw : 0 bit name lsb first overrun spi complete tx reg empty rx reg full clock phase clock polarity enable bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 193 usb_sof0 0,31h 21.3.6 usb_sof0 usb start-of-frame register 0 this register is a usb start-of-frame register 0. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7:0 frame number[7:0] contains the lower eight bits of the frame number. individual register names and addresses: 0,31h usb_sof0 : 0,31h 7 6 5 4 3 2 1 0 access : por r : 00 bit name frame number[7:0] bit name description [+] feedback
194 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c usb_sof1 0,32h 21.3.7 usb_sof1 usb start-of-frame register 1 this register is a usb start-of-frame register 1. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 2:0 frame number[10:8] contains the upper three bits of the frame number. individual register names and addresses: 0,32h usb_sof1 : 0,32h 7 6 5 4 3 2 1 0 access : por r : 0 bit name frame number[10:8] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 195 usb_cr0 0,33h 21.3.8 usb_cr0 usb control register 0 this register is a usb control register 0. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7 usb enable this bit enables the psoc devic e to respond to usb traffic. 0 usb disabled. 1 usb enabled. 6:0 device address these bits specify the usb addr ess to which the sie responds. individual register names and addresses: 0,33h usb_cr0 : 0,33h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 00 bit name usb enable device address[6:0] bit name description [+] feedback
196 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c usbio_cr0 0,34h 21.3.9 usbio_cr0 usb i/o control register 0 this register is a usbio manual control register 0. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7ten transmit enable. this bit is used to manually transmit on d+, d- pi ns. normally, this bit must be cleared to allow the internal sie to drive the pi ns. the most common reason for manually transmitting is to force a resume state on the bus. 0 manual transmission off. 1 manual transmission enabled. 6 tse0 both d+ and d- are low. there is no effect if ten=0. 5td this bit transmits a usb j or k state on the us b bus. there is no effect if ten=0 or tse0=1. 0 force usb k state. 1 force usb j state. 0rd this read only bit gives the state of the usb differential receiver. 0 d+ < d- or d+ = d- = 0. 1 d+ > d-. individual register names and addresses: 0,34h usbio_cr0 : 0,34h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 r : 0 bit name ten tse0 td rd bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 197 usbio_cr1 0,35h 21.3.10 usbio_cr1 usb i/o control register 1 this register is a usbio manual control register 1. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7 iomode this bit allows the configuration of d+ and d- pins. 6 drive mode this bit configures d+ and d- pins fo r either cmos drive or open drain drive. 5dpi this bit drives the d+ pin if iomode=1. 4dmi this pin drives the d- pin if iomode=1. 3 ps2puen this bit controls the connection of the two internal 5 k pull up resistors to the d+ and d- pins. 2 usbpuen this bit controls the connec tion of the internal 1.5 k pull up resistor on the d+ pin. 1dpo this read only bit provi des the d+ pin status. 0dmo this read only bit provides the d- pin status. individual register names and addresses: 0,35h usbio_cr1 : 0,35h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 r :1 r : 1 bit name iomode drive mode dpi dmi ps2puen usbpuen dpo dmo bit name description [+] feedback
198 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c ep0_cr 0,36h 21.3.11 ep0_cr endpoint 0 control register this register is an endpoint 0 control register. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7 setup received when set, this bit indicates a valid setup packet was received and ack?ed. 6 in received when set, this bit indicates a valid in packet was received. 5 out received when set, this bit indicates an out packet was received. 4 ack?ed transaction when set, this bit indicates a vali d out packet has been received and ack?ed. 3:0 mode[3:0] the mode bits control how the usb sie responds to traffic and how the usb sie changes the mode of that endpoint as a result of host packets to the endpoint. individual register names and addresses: 0,36h ep0_cr : 0,36h 7 6 5 4 3 2 1 0 access : por rc : 0 rc : 0 rc : 0 rc : 0 rw : 0 bit name setup received in received out received ack?ed transaction mode[3:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 199 ep0_cnt 0,37h 21.3.12 ep0_cnt endpoint 0 count register the endpoint 0 count register (ep0_cnt) configures endpoint 0. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7 data toggle this bit selects the data packet's toggle state. 6 data valid this bit indicates whether there were errors in out or setup transactions. 3:0 byte count[3:0] these bits indicate the number of data bytes in a transaction. individual register names and addresses: 0,37h ep0_cnt : 0,37h 7 6 5 4 3 2 1 0 access : por rw : 0 rc : 0 rw : 0 bit name data toggle data valid byte count[3:0] bit name description [+] feedback
200 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c ep0_drx 0,38h 21.3.13 ep0_drx endpoint 0 data registers these registers are endpoint 0 data registers. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7:0 data byte[7:0] these registers are shared for both transmit and receive. individual register names and addresses: 0,38h ep0_dr0 : 0,38h ep0_dr1 : 0,39h ep0_dr2 : 0,3ah ep0_dr3 : 0,3bh ep0_dr4 : 0,3ch ep0_dr5 : 0,3dh ep0_dr6 : 0,3eh ep0_dr7 : 0,3fh 7 6 5 4 3 2 1 0 access : por rw : 00 bit name data byte[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 201 epx_cnt0 0,40h 21.3.14 epx_cnt0 endpoint count 0 registers these registers are endpoi nt count 0 registers. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7 data toggle this bit selects the data packet's toggle state. 6 data valid this bit is used for out trans actions only and is read only. 0 count msb this bit is the 1 msb of a 9-bit counter. individual register names and addresses: 0,40h ep1_cnt0 : 0,40h ep2_cnt0 : 0,42h ep3_cnt0 : 0,44h ep4_cnt0 : 0,46h ep5_cnt0 : 0,48h ep6_cnt0 : 0,4ah ep7_cnt0 : 0,4ch ep8_cnt0 : 0,4eh 7 6 5 4 3 2 1 0 access : por rw : 0 rc : 0 # : 0 bit name data toggle data valid count msb bit name description [+] feedback
202 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c epx_cnt1 0,41h 21.3.15 epx_cnt1 endpoint count 1 registers these registers are endpoi nt count 1 registers. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7:0 data count[7:0] these bits are the eight lsb of a 9-bit counter. t he msb is the count msb of the epx_cnt0 register. individual register names and addresses: 0,41h ep1_cnt1 : 0,41h ep2_cnt1 : 0,43h ep3_cnt1 : 0,45h ep4_cnt1 : 0,47h ep5_cnt1 : 0,49h ep6_cnt1 : 0,4bh ep7_cnt1 : 0,4dh ep8_cnt1 : 0,4fh 7 6 5 4 3 2 1 0 access : por rw : 00 bit name data count[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 203 pmax_dr 0,58h 21.3.16 pmax_dr psoc memory arbite r data registers these registers are psoc memory arbiter write address registers. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7:0 data byte[7:0] when the m8c writes to this register, the pma registers the byte and then stores the value at the address in sram indicated by the pmax_wa register. individual register names and addresses: 0,58h pma0_dr : 0,58h pma1_dr : 0,59h pma2_dr : 0,5ah pma3_dr : 0,5bh pma4_dr : 0,5ch pma5_dr : 0,5dh pma6_dr : 0,5eh pma7_dr : 0,5fh pma8_dr : 0,64h pma9_dr : 0,65h pma10_dr : 0,66h pma11_dr : 0,67h pma12_dr : 0,68h pma13_dr : 0,69h pma14_dr : 0,6ah pma15_dr : 0,6bh 7 6 5 4 3 2 1 0 access : por rw : 00 bit name data byte[7:0] bit name description [+] feedback
204 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c amux_cfg 0,61h 21.3.17 amux_cfg analog mux confi guration register this register is used to configure the integration capacitor pin connections to the analog global bus. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 100 in the i/o analog mux chapter. 5prx_mode when this bit is set to 1, cs_clk from truetouch counter logic block toggles regardless of the "en" bit setting in cs_cr0 register. when this bit is 0 cs _clk is gated by "en" bit in cs_cr0 register. this bit is typically used in proximity detection mode. 3:2 icapen[1:0] bits connect internal capacit ance to the analog global bus. 00b no capacitance 01b approximately 25 pf connected 10b approximately 50 pf connected 11b approximately 100 pf connected 1:0 intcap[1:0] select pins to enable connection of external integration capacitor in the charge integration mode. 00b neither p0[3] or p0[1] enabled 01b p0[1] pin enabled 10b p0[3] pin enabled 11b both p0[3] and p0[1] pins enabled individual register names and addresses: 0,61h amux_cfg : 0,61h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name prx_mode icapen[1:0] intcap[1:0] bits name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 205 cmp_rdc 0,78h 21.3.18 cmp_rdc comparator read/clear register this register is used to read the state of the comparator data signal and the latched state of the comparator. in the table above, reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 103 in the comparators chapter. 5cmp1d read only bit that returns the dynamically changing state of comparator 1. this bit reads zero when- ever the comparator is disabled. 4cmp0d read only bit that returns the dynamically changing state of comparator 0. this bit reads zero when- ever the comparator is disabled. 1cmp1l this bit reads the latch output for comparator 1. it is cleared by either a write of ?0? to this bit, or by a rising edge of the comparator 0 lut, depending on the state of the crst1 bit in the cmp_cr1 reg- ister. 0cmp0l this bit reads the latch output for comparator 0. it is cleared by either a write of ?0? to this bit, or by a rising edge of the comparator 1 lut, depending on the state of the crst0 bit in the cmp_cr1 reg- ister. individual register names and addresses: cmp_rdc : 0,78h 0,78h 7 6 5 4 3 2 1 0 access : por r : 0 r : 0 rc : 0 rc : 0 bit name cmp1d cmp0d cmp1l cmp0l bit name description [+] feedback
206 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cmp_mux 0,79h 21.3.19 cmp_mux comparator multiplexer register this register contains control bits for input selection of comparators 0 and 1. for additional information, refer to the register definitions on page 103 in the comparators chapter . 7:6 inp1[1:0] comparator 1 positive input select 00b analog global mux bus 01b reserved 10b p0[1] pin 11b p0[3] pin 5:4 inn1[1:0] comparator 1 negative input select 00b vref (1.0v) 01b ref lo (approximately 0.6v) 10b ref hi (approximately 1.2v) 11b reserved 3:2 inp0[1:0] comparator 0 positive input select 00b analog global mux bus 01b reserved 10b p0[1] pin 11b p0[3] pin 1:0 inn0[1:0] comparator 0 negative input select 00b vref (1.0v) 01b ref lo (approximately 0.6v) 10b ref hi (approximately 1.2v) 11b reserved individual register names and addresses: 0,79h cmp_mux : 0,79h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 bit name inp1[1:0] inn1[1:0] inp0[1:0] inn0[1:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 207 cmp_cr0 0,7ah 21.3.20 cmp_cr0 comparator control register 0 this register is used to enable and configure the input range of the comparators. in the table above, reserved bits are grayed table cells and ar e not described in the bit description section below. always wri te reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 103 in the comparators chapter . 4cmp1en 0 comparator 1 disabled, powered off. 1 comparator 1 enabled. 0cmp0en 0 comparator 0 disabled, powered off. 1 comparator 0 enabled. individual register names and addresses: 0,7ah cmp_cr0 : 0,7ah 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 bit name cmp1en cmp0en bit name description [+] feedback
208 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cmp_cr1 0,7bh 21.3.21 cmp_cr1 comparator control register 1 this register is used to configure the comparator output options. for additional information, refer to the register definitions on page 103 in the comparators chapter . 7cint1 this bit selects comparator 1 for input to the analog interrupt. note that if both cint1 and cint0 are set high, a rising edge on either comparator output may cause an interrupt. 0 comparator 1 does not connect to the analog interrupt. 1 comparator 1 connects to the analog interrupt. a rising edge asserts that interrupt, if it is enabled in the int_msk0 register. 6cpin1 this bit selects the comparator 1 signal for possibl e connection to the gpio pin. connection to the pin also depends on the configurat ion of the out_p1 register. 0 select comparator 1 lut output. 1 select comparator 1 latch output. 5 crst1 this bit selects the source for resetting the comparator 1 latch. 0 reset by writing a ?0? to the cmp_rdc register?s cmp1l bit. 1 reset by rising edge of comparator 0 lut output. 4 cds1 this bit selects the data output for the comparator 1 channel, for routing to the capacitive sense logic and comparator 1 interrupt. 0 select the comparator 1 lut output. 1 select the comparator 1 latch output. 3cint0 this bit selects comparator 0 for input to the analog interrupt. note that if both cint1 and cint0 are set high, a rising edge on either comparator output may cause an interrupt. 0 comparator 0 does not connect to the analog interrupt. 1 comparator 0 connects to the analog interrupt. a rising edge asserts that interrupt, if it is enabled in the int_msk0 register. 2cpin0 this bit selects the comparator 0 signal for possibl e connection to the gpio pin. connection to the pin also depends on the configurat ion of the out_p1 register. 0 select comparator 0 lut output. 1 select comparator 0 latch output. 1 crst0 this bit selects the source for resetting the comparator 0 latch. 0 reset by writing a ?0? to the cmp_rdc register?s cmp0l bit. 1 reset by rising edge of comparator 1 lut output. (continued on next page) individual register names and addresses: 0,7bh cmp_cr1 : 0,7bh 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name cint1 cpin1 crst1 cds1 cint0 cpin0 crst0 cds0 bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 209 cmp_cr1 0,7bh 21.3.21 cmp_cr1 (continued) 0 cds0 this bit selects the data output for the comparator 0 channel, for routing to the capacitive sense logic and comparator 0 interrupt. 0 select the comparator 0 lut output. 1 select the comparator 0 latch output. [+] feedback
210 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cmp_lut 0,7ch 21.3.22 cmp_lut comparator lut register this register is used to select the logic function. for additional information, refer to the register definitions on page 103 in the comparators chapter. 7:4 lut1[3:0] select 1 of 16 logic functions for output of comparator bus 1. a=comp1 output, b=comp0 output. function 0h false 1h a and b 2h a and b 3h a 4h a and b 5h b 6h a xor b 7h a or b 8h a nor b 9h a xnor b ah b bh a or b ch a dh a or b eh a nand b fh true 3:0 lut0[3:0] select 1 of 16 logic functions for output of co mparator bus 0. a=comp0 output, b=comp1 output. function 0h false 1h a and b 2h a and b 3h a 4h a and b 5h b 6h a xor b 7h a or b 8h a nor b 9h a xnor b ah b bh a or b ch a dh a or b eh a nand b fh true individual register names and addresses: 0,7ch cmp_lut : 0,7ch 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 bit name lut1[3:0] lut0[3:0] bits name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 211 cs_cr0 0,a0h 21.3.23 cs_cr0 truetouch contro l register 0 this register controls the operation of the truetouch counters. do not write bits [7:1] while the block is enabled. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 7:6 csout[1:0] these bits select between a number of truetouch signals that can be driven to an output pin. 00b in. 01bcs_int. 10bcol. 11bcoh. 5 csd_prsclk this bit selects between imo-p or the prs output as a clock source to drive the main capacitor switch. 0 select imo-p. 1 select prs output. 4 csd_cs_clk this bit selects between imo or imo-p for the truetouch counters to work. depending on this bit selection either imo or imo-p is sent as the source clock to the clock dividers which generate cs_clk as shown in figure 11-13 on page 91 . 0 select imo. 1 select imo-p. 3csd_mode this bit enables the csd mode. when this bit is enabled, the timer1 block works on imo-p (pre- scaled imo) clock. this is also an enable for truetouch counters to toggle. note : once the csd_mode bit is enabled, the imo- p clock is a free ru nning divider clock that cannot be stopped and re-started. the imo-p and the cpu clock are both derived from the imo clock but the phase relationship between them is nondeterministic. 0 disable csd mode. programmable timer1 works on either cpuclk/clk32, (depends on clksel bit selection in pt 1_cfg (0, b3h) register). 1 enable csd mode. when this bit is set to 1, programmable timer1 works on imo-p. 2:1 mode[1:0] truetouch counter mode. 00b event mode. start in enable, stop on interrupt event. 01b pulse width mode. start on positive edge of next input. stop on negative edge of input. 10b period mode. start on positive edge of input. stop on next positive edge of input. 11b start in enable, continuous operation until disable. 0en 0 counting is stopped and all counter values are reset to zero. 1 counters are enabled for counting. individual register names and addresses: 0,a0h cs_cr0 : 0,a0h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name csout[1:0] csd_ prsclk csd_cs_ clk csd_ mode mode[1:0] en bit name description [+] feedback
212 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cs_cr1 0,a1h 21.3.24 cs_cr1 truetouch control register 1 this register contains additional truetouch system control options. never write to this register while the block is enabled. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 7 chain counter chain control. 0 8-bit high/low counters operate independently. 1 high/low counters operate as a 16-bit synchronous block. 6:5 clksel[1:0] truetouch clock (csclk) selection. 00b imo. 01b imo/2. 10b imo/4. 11b imo/8. 4rloclk relaxation oscillator clock (rlo) select. 0 high byte counter runs on the selected imo-based frequency. 1 high byte counter runs on the rlo clock frequency. 3inv input invert. 0 selected input is not inverted. 1 selected input is inverted. 2:0 insel[2:0] input selection. 000b comparator 0. 001b ilo. 010b comparator 1. 011b rlo timer terminal count. 100b interval timer. 101b rlo timer irq. 110b analog global mux bus. 111b ?0?. individual register names and addresses: 0,a1h cs_cr1 : 0,a1h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name chain clksel[1:0] rloclk inv insel[2:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 213 cs_cr2 0,a2h 21.3.25 cs_cr2 truetouch contro l register 2 this register contains additional truetouch system control options. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 7:6 irange bits scale the idac current output. the idac_d register sets the base current in the idac. 00b idac output scaled to 1x range. 01b idac output scaled to 2x range. 10b idac output scaled to 4x range. 11b idac output scaled to 8x range. 5 idacdir bit determines the source/sink state of the id ac when enabled (idac_en = 1 or pxd_en = 1 or csd_mode = 1). 0 idac sources current to analog global bus. 1 idac sinks current from analog global bus. 4 idac_en bit provides manual connection of the idac to t he analog global bus. the idac is automatically con- nected when ro_en = 1 or pxd_en = 1. 0 no manual connection. 1 idac is connected to analog global bus. 3cin_en 0 negative charge integration disabled. 1 negative charge integration enabled. selected s ense pin(s) alternately connect to the ana- log global bus and ground. clock ra te is selected by the clksel bits in the cs_cr1 regis- ter. 2 pxd_en 0 no clock to i/o pins. 1 enabled pins switch between ground and the analog global bus. clock rate selected by the clksel bits in the cs_cr1 register. selected clock drives truetouch timer. 1 cip_en 0 positive charge integration disabled. 1 positive charge integration enabled. reference buffer and integration capacitor pins alter- nately connect to analog global bus. clock rate selected by the clksel bits in the cs_cr1 register. 0 ro_en 0 relaxation oscillator disabled. 1 relaxation oscillator enabled. charging cu rrents are set by the irange bits and the idac_d register value. individual register names and addresses: 0,a2h cs_cr2 : 0,a2h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name irange idacdir idac_en cin_en pxd_en cip_en ro_en bit name description [+] feedback
214 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cs_cr3 0,a3h 21.3.26 cs_cr3 truetouch control register 3 this register contains control bits primarily for the proximity detection algorithm. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 6refmux this bit selects the reference voltage for the input of the reference buffer. 0 select refhi (1.2v). 1 select vref (1.0v). 5refmode this bit allows manual connection of the referenc e buffer output to the analog global bus. if either ci_en = 1 or ro_en = 1 in the cs_cr2 register, th is bit has no effect (reference buffer connection is off or controlled by other settings). 0 no connection. 1 reference buffer connected to the analog global bus. 4ref_en this bit enables the reference bu ffer to drive the analog global bus. 0 reference buffer is disabled, powered down. 1 reference buffer is enabled. connection to t he analog global bus is c ontrolled by the ref- mode bit in this register, and by the ci_e n and ro_en bits in the cs_cr2 register. 3:2 lpfilt[1:0] low pass filter approximate time constant. 00b 1 s 01b 2 s 10b 5 s 11b 10 s 1:0 lpf_en[1:0] enable this bit for the low pass filter. 00b no connection of either comparator channel to low pass filter. 01b connect comparator channel 0 through the low pass filter. 10b connect comparator channel 1 through the low pass filter. 11b connect both comparator channel inputs together, and through the low pass filter. individual register names and addresses: 0,a3h cs_cr3 : 0,a3h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name refmux refmode ref_en lpfilt[1:0] lpf_en[1:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 215 cs_cntl 0,a4h 21.3.27 cs_cntl truetouch counter low byte register this register contains the current count for the low byte counter and is read only. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 7:0 data[7:0] on a read of this register, the current count is returned. it may only be read when the counter is stopped. note the counter must be stopped by the configured ev ent. when the counter is disabled, the count is reset to 00h. individual register names and addresses: 0,a4h cs_cntl : 0,a4h 7 6 5 4 3 2 1 0 access : por ro : 00 bit name data[7:0] bit name description [+] feedback
216 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cs_cnth 0,a5h 21.3.28 cs_cnth truetouch counter high byte register this register contains the current count value for the high byte counter and is read only. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 7:0 data[7:0] on a read of this register, the current count is re turned. it is only read when the counter is stopped. note the counter must be stopped by the configured ev ent. when the counter is disabled, the count is reset to 00h. individual register names and addresses: 0,a5h cs_cnth : 0,a5h 7 6 5 4 3 2 1 0 access : por ro : 00 bit name data[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 217 cs_stat 0,a6h 21.3.29 cs_stat truetouch status register this register controls the truetouch counter options. never modify the interrupt mask bits while the block is enabled . if a modification to bits 3 to 0 is necessary while the block is enabled, then pay close attention to ensure that the status bits 7 to 4, are not accidentally cleared. you do this by writing a ?1? to all of the status bits when writing to the mask bits. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 7ins input status. 0 no event detected. 1 a rising edge on the selected input was detec ted. cleared by writing a ?0? to this bit. 6cols counter carry out low status. 0 no event detected. 1 a carry out from low byte counter was detected. cleared by writing a ?0? back to this bit. 5cohs counter carry out high status. 0 no event detected. 1 a carry out from high byte counter was detect ed. cleared by writing a ?0? back to this bit. 4 pps pulse width/period measurement status. 0 no event detected. 1 a pulse width or period measurement was comp leted. cleared by writing a ?0? back to this bit. 3inm input interrupt/mask. 0 disabled. 1 input event is enabled to as sert the block interrupt. 2colm counter carry out low interrupt mask. 0 disabled. 1 counter carry out low is enabled to assert the block interrupt. 1cohm counter carry out high interrupt mask. 0 disabled. 1 counter carry out high is enabled to assert the block interrupt. 0 ppm pulse width/period measurement interrupt mask. 0 disabled. 1 completion of a pulse width or period measurem ent is enabled to assert the block interrupt. individual register names and addresses: 0,a6h cs_sta t : 0,a6h 7 6 5 4 3 2 1 0 access : por rc : 0 rc : 0 rc : 0 rc : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name ins cols cohs pps inm colm cohm ppm bit name description [+] feedback
218 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cs_timer 0,a7h 21.3.30 cs_timer truetouch timer register this register sets the timer count value. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 6:0 timer count value[6:0] holds the timer count value. individual register names and addresses: 0,a7h cs_timer : 0,a7h 7 6 5 4 3 2 1 0 access : por rw : 00 bit name timer count value [6:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 219 cs_slew 0,a8h 21.3.31 cs_slew truetouch slew control register this register enables and controls a fast slewing mode for the relaxation oscillator. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 7:1 fastslew[6:0] this 7-bit value sets a counter , clocked at the imo frequency. wh ile the counter is counting down from this value, the relaxation oscillator edge slew s at the maximum gain setting. during this interval, the irange bits in the cs_cr2 register are inter nally set to maximum (11b). at the end of the inter- val, the user-defined irange level is restored so that the relaxation oscillat or continues slewing with a slower edge rate to the target voltage threshold. if the fs_en bit is low, the fastslew setting has no effect. after each edge of the relaxation oscillator, the coun ter is re-loaded and the fast slewing interval re- occurs, followed by the slower edge rate at the end of the count down. note that the irange bits in the cs_cr2 regist er always read the user-defined setting. because the irange value is forced to maximum during this in terval, the increase in the edge rate can be 1x, 2x, 4x, or 8x, depending on the programmed value of the irange bits. 0000000b no fast edge rate interval. 0000001b minimum fast edge rate interval (1 imo period). ? 1111111b maximum fast edge rate interval (127 imo period). 0 fs_en enable bit for the fast slew mode. 0 fast slew mode disabled. 1 fast slew mode enabled. after each relaxation os cillator transition, the relaxation oscillator runs with a higher current for a time controlled by the fastslew bits. individual register names and addresses: 0,a8h cs_slew : 0,a8h 7 6 5 4 3 2 1 0 access : por rw : 00 rw : 0 bit name fastslew[6:0] fs_en bit name description [+] feedback
220 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c prs_cr 0,a9h 21.3.32 prs_cr pseudo ransom sequence and prescaler control register this register controls the prescaler and pseudo random sequenc e generator output. for additional information, refer to the register definitions on page 92 in the truetouch module chapter . 7 cs_clk_out this bit selects the truetouch clock (inversion or non-inversion depending on bit 6 setting) to be routed onto primary pin depending on the out_p1/out_p0 register selection. 1 route prescaler output or prs output depending on csd_prsclk in cs_cr0 when in csd mode, or route clock based on clksel bits in cs_cr1 register in normal truetouch mode to primary pins p1[2]/p0[7] depending on out_p1/out_p0 bit selections instead of normal csout[ selections. see out_ p1/out_p0 registers for details. 0 use csout [1:0] selections as normal. 6 cs_clk_inv this bit allows you to route either truetouch cl ock or inversion of the truetouch clock onto pin. 1 inverted truetouch clock r outes to pin (see bit 7). 0 non-inverted truetouch clock routes to pin (see bit 7). 5 prs_12bit this bit allows selection between 8-bit prs or 12-bit prs output. 0 msb of 8-bit prs is sent out. 1 msb of 12-bit prs is sent out 4prs_en this bit is used to enable or disable the prs block. 0 prs is disabled. prs block output is '0'. 1 prs is enabled and the bit 5 decides whether msb of 12-bit prs is sent out or msb of 8-bit prs is sent out. 3 prescalebyp this bit is used to bypass the prescaler and pa ss the input clock undivided onto the output. the out- put of the prescaler feeds the clock input to the prs block. 0 divided clock is sent out of prescaler depending on bit [2:0] setting. 1 incoming imo clock is sent out of prescaler without any division. 2:0 prescale_clk_div[2:0] these bits allow for of one of eight frequencies of incoming imo clock to be fed as input to prs. 000 divides the input imo clock by 2. 001 divides the input imo clock by 4. 010 divides the input imo clock by 8. 011 divides the input imo clock by 16. 100 divides the input imo clock by 32. 101 divides the input imo clock by 64. 110 divides the input imo clock by 128. 111 divides the input imo clock by 256. individual register names and addresses: 0,a9h prs_cr : 0,a9h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0? rw : 0? rw : 0 rw : 0 rw : 0 bit name cs_clk_out cs_clk_inv prs_12bit prs_en prescale- byp prescale_clk_div[2:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 221 pt0_cfg 0,b0h 21.3.33 pt0_cfg programmable timer 0 co nfiguration register this register configures the programmable timer 0. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 163 in the programmable timer chapter . 2clksel this bit determines if the timer runs on the 32 khz cloc k or cpu clock. if the bit is set to 1'b1, the timer runs on the cpu clock, otherwise, the timer runs on the 32 khz clock. 1one shot 0 continuous count mode. timer reloads the c ount value from the data registers upon each terminal count, and continues counting. 1 one-shot mode. timer goes through one complete count period and then stops. upon com- pletion, the start bit in this register is cleared. 0start 0 timer held in reset. 1 timer counts down from a full count determined from its data registers (pt_data1, pt_data0). when complete, it either stops or reloads and continues, based on the one shot bit in this register. individual register names and addresses: 0,b0h pt0_cfg : 0,b0h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name clksel one shot start bit name description [+] feedback
222 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c ptx_data1 0,b1h 21.3.34 ptx_data1 programmable timers data register 1 these registers hold the eight bits of the pr ogammable timer?s count value for the device. for additional information, refer to the register definitions on page 163 in the programmable timer chapter . 7:0 data[7:0] this is the upper byte of a 16-bit timer. the lo wer byte is in the corresponding ptx_data0 register. individual register names and addresses: 0,b1h pt0_data1 : 0,b1h pt1_data1 : 0,b4h pt2_data 1 : 0,b7h 7 6 5 4 3 2 1 0 access : por rw : 00 bit name data[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 223 ptx_data0 0,b2h 21.3.35 ptx_data0 programmable timers data register 0 these registers provide the progr ammable timer with its lower eight bits of the count value. for additional information, refer to the register definitions on page 163 in the programmable timer chapter . 7:0 data[7:0] this is the lower byte of a 16-bit timer. the upper byte is in the corresponding ptxdata1 register. individual register names and addresses: 0,b2h pt0_data 0 : 0,b2h pt1_data0 : 0,b5h pt2_data0 : 0,b8h 7 6 5 4 3 2 1 0 access : por rw : 00 bit name data[7:0] bit name description [+] feedback
224 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c pt1_cfg 0,b3h 21.3.36 pt1_cfg programmable timer 1 co nfiguration register this register configures the programmable timer 1. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 163 in the programmable timer chapter . 2clksel this bit determines if the timer runs on the 32 khz clo ck or cpu clock. if the bit is set to 1'b1, the timer runs on the cpu clock, otherwise, the timer runs on the 32 khz clock. 1 one shot 0 continuos count mode. timer reloads the c ount value from the data registers upon each terminal count, and continues counting. 1 one-shot mode. timer goes through one complete count period and then stops. upon com- pletion, the start bit in this register is cleared. 0start 0 timer held in reset. 1 timer counts down from a full count determined from its data registers (pt_data1, pt_data0). when complete, it either stops or reloads and continues, based on the one shot bit in this register. individual register names and addresses: 0,b3h pt1_cfg : 0,b3h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name clksel one shot start bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 225 pt2_cfg 0,b6h 21.3.37 pt2_cfg programmable timer 2 co nfiguration register this register configures the programmable timer 2. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 163 in the programmable timer chapter . 2clksel this bit determines if the timer runs on the 32 khz cloc k or cpu clock. if the bit is set to 1'b1, the timer runs on the cpu clock, otherwise, the timer runs on the 32 khz clock. 1one shot 0 continuous count mode. timer reloads the c ount value from the data registers upon each terminal count, and continues counting. 1 one-shot mode. timer goes through one complete count period and then stops. upon com- pletion, the start bit in this register is cleared. 0start 0 timer held in reset. 1 timer counts down from a full count determined from its data registers (pt_data1, pt_data0). when complete, it either stops or reloads and continues, based on the one shot bit in this register. individual register names and addresses: 0,b6h pt2_cfg : 0,b6h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name clksel one shot start bit name description [+] feedback
226 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c_xcfg 0,c8h 21.3.38 i2c_xcfg i 2 c extended configuration register this register configures enhanced features. the enable bit (bit 0) of the i2c_cfg (0,d6h) register should be set to 1'b1 for the i2c enhanced features to work. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. always write reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 122 in the i2c slave chapter . 3 no bc int in compatibility mode, every received or transmitt ed byte generates a byte complete interrupt. this is also true in buffered mode regardless of whether the bus is stalled or not. note when this bit is set to a ?1?, a bc interrupt is not enabled for any data byte that is automatically ack?ed (i.e., does not require the bus to stall). a bc interrupt is always generated upon any stall so the cpu takes the appropriate action. when the bit is set, it is possible to implement packet transfers without cpu intervention by enabling an interrupt upon the stop detect. 1 buffer mode this bit determines the operation mode of the enhanced buffer module. the fo llowing table describes the available modes. 0hw addr en when this bit is set to a ?1?, hardware address compare is enabled. when enabled, bit 3 in the i2c_scr register is not set. upon a compare, t he address is automatically ack?ed, and upon a mis- match, the address is automatically nack?ed and the hardware reverts to an idle state waiting for the next start detection. you must configure the com pare address in the i2c_addr register. when this bit is a ?0?, bit 3 of the i2c_s cr register is set and the bus stal ls, and the received address is avail- able in the i2c_dr register to enable the cpu to do a firmware address compare. the functionality of this bit is independent of the data buffering mode. individual register names and addresses: 0,c8h i2c_xcfg: 0,c8h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name no bc int buffer mode hw addr en bit name description buffer mode name description 0 compatible there is no buffering in the default compatibility mode. the i2c bus is stalled upon every received or transmitted byte, including address bytes. the cpu is required to process the interrupt and write or read the data and status as required to continue the operation. 1ezi2c the i2c slave appears as a 32-byte ram interface to an external master. a specific protocol must be followed, in which the master controls the ram pointer for both read and write operations. the i2c bus is never stalled. receive acks are automati- cally generated. the cpu is responsible for putting valid data into the ram for external reads, and for reading received data. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 227 i2c_xstat 0,c9h 21.3.39 i2c_xstat i 2 c extended status register this register reads enhanced feature status. when the bits of the i2c_xcfg register are left in their reset state, the block is in compatibility mode and this register is not in use. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. always write reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 122 in the i2c slave chapter. 1dir this bit indicates the dire ction of the current transfer. a ?1? indicates a master read, and a ?0? indicates a master write. it is only valid when the slave busy bit (bit 0) is set to a ?1?. 0 slave busy this bit is set upon a hardware compare and is rese t upon the following stop signal. poll this bit to determine when the slave is busy an d the buffer module is being accessed. individual register names and addresses: 0,c9h 0,d0h i2c_xstat : 0,c9h 7 6 5 4 3 2 1 0 access : por r : 0 r : 0 bit name dir slave busy bit name description [+] feedback
228 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c_addr 0,cah 21.3.40 i2c_addr i 2 c slave address register this register holds the slave?s 7-bit address. when hardware address compare mode is not enabled in the i2c_xcfg register, this register is not in use. in the table above, note that the reserved bit is a grayed table cell and not described in the bit description section below. always write reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 122 in the i2c slave chapter. 6:0 slave address[6:0] these seven bits hold the slave?s own device address. individual register names and addresses: 0,cah 0,d0h i2c_addr : 0,cah 7 6 5 4 3 2 1 0 access : por rw : 00 bit name slave address[6:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 229 i2c_bp 0,cbh 21.3.41 i2c_bp i 2 c base address pointer register this register contains the base address value of the ram data buffer and is read only. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. always write reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 122 in the i2c slave chapter. 4:0 i2c base pointer[4:0] in the ezi2c protocol, the first data byte after t he slave address transaction in write mode is the base address for subsequent reads and writes and it is trans ferred directly into this register. if the desired transaction is a master write to the slave, subsequent bytes are written to the ram buffer starting with this address and auto incremented (see i2c_cp register). in case of a read, a start or restart must be issued and the read location starts with th is address and again subsequent read addresses are auto incremented as pointed to by the i2c_cp register value. the value of this register is m odified only at the beginning of ever y i2c write transaction. the i2c master must always supply a value for this register in the first byte of data after the slave?s address in a given write transaction. if performing reads, the ma ster need not set the value of this register. the current value of this register is also used directly for reads. individual register names and addresses: 0,cbh 0,d0h i2c_bp : 0,cbh 7 6 5 4 3 2 1 0 access : por r : 00 bit name i2c base pointer[4:0] bit name description [+] feedback
230 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c_cp 0,cch 21.3.42 i2c_cp i 2 c current address pointer register this register contains the current address value of the ram data buffer and is read only. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. always write reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 122 in the i2c slave chapter. 4:0 i2c current pointer[4:0] this register is set at the same time and with the same value to which the i2c_bp register is set. after each completed data byte of the current i2c transacti on, the value of this register is incremented by one. the value of this register always determines the location that read or write data comes from or is written to. this register is set to the value contained in the i2 c_bp register on every start condition detected in the bus. individual register names and addresses: 0,cch i2c_cp : 0,cch 7 6 5 4 3 2 1 0 access : por r : 00 bit name i2c current pointer[4:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 231 cpu_bp 0,cdh 21.3.43 cpu_bp cpu base address pointer register this register contains the base address value of the ram data buffer. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. always write reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 122 in the i2c slave chapter. 4:0 cpu base pointer[4:0] this register value is completely controlled by i/o writes by the cpu. firmware routines must set this register. similar to the i2c_bp_wr, the value of th is register sets the starting address for the data location being written to or read from. when this register is written, the current address pointer cpu_cp is also updated with the same value. the first read or write from/to the i2c_ buf register starts at this address. the location of the data in subsequent read or writes is determined by the cpu_cp register value, which auto increments afte r each read or write. firmware makes certain that the slave device always has valid data or the data is read before overwritten. individual register names and addresses: 0,cdh cpu_bp : 0,cdh 7 6 5 4 3 2 1 0 access : por rw : 00 bit name cpu base pointer[4:0] bit name description [+] feedback
232 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cpu_cp 0,ceh 21.3.44 cpu_cp cpu current address pointer register this register is a pointer into the ram buffer for cpu reads and writes and is read only. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. always write reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 122 in the i2c slave chapter. 4:0 cpu current pointer[4:0] this register is set at the same time and with the same value to which the cpu_bp register is set. whenever the i2c_buf register is written to or read from, the cpu_cp automatically increments . individual register names and addresses: 0,ceh cpu_cp : 0,ceh 7 6 5 4 3 2 1 0 access : por r : 00 bit name cpu current pointer [4:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 233 i2c_buf 0,cfh 21.3.45 i2c_buf i 2 c data buffer register this register is the cpu read/write interface to the data buffer. for additional information, refer to the register definitions on page 122 in the i2c slave chapter. 7:0 data buffer[7:0] the i2c data buffer register (i2c_buf) is the cp u read/write interface to the data buffer. whenever this register is read, the data at the location poin ted to by cpu current pointer (cpu_cp) is returned. similarly, whenever this register is written, the data is transferred to the buffer and written at the loca- tion pointed to by the cpu current pointer (cpu_cp). wh enever this register is read without initializ- ing the ram contents either through the i2c or cpu interface, no valid value is returned. individual register names and addresses: 0,cfh i2c_buf : 0,cfh 7 6 5 4 3 2 1 0 access : por rw : 00 bit name data buffer [7: 0] bit name description [+] feedback
234 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cur_pp 0,d0h 21.3.46 cur_pp current page pointer register this register is used to set the effective sram page for nor mal memory accesses in a multi- sram page device. it is only used when a device has more than one sram page. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 42 in the ram paging chapter . 2:0 page bits[2:0] bits determine which sram page is used for generic sram access. see the ram paging chapter on page 39 for more information. 000b sram page 0 001b sram page 1 010b sram page 2 011b sram page 3 100b sram page 4 101b sram page 5 110b sram page 6 111b sram page 7 individual register names and addresses: 0,d0h cur_pp : 0,d0h 7 6 5 4 3 2 1 0 access : por rw : 0 bit name page bits[2:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 235 stk_pp 0,d1h 21.3.47 stk_pp stack page pointer register this register is used to set the effective sram page for stack memory accesses in a multi-sram page psoc device. it is only used when a device has more than one sram page. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 42 in the ram paging chapter . 2:0 page bits[2:0] bits determine which sram page is used to hold the stack. see the ram paging chapter on page 39 for more information. 000b sram page 0 001b sram page 1 010b sram page 2 011b sram page 3 100b sram page 4 101b sram page 5 110b sram page 6 111b sram page 7 individual register names and addresses: 0,d1h stk_pp : 0,d1h 7 6 5 4 3 2 1 0 access : por rw : 0 bit name page bits[2:0] bit name description [+] feedback
236 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c idx_pp 0,d3h 21.3.48 idx_pp indexed memory access page pointer register this register is used to set the effective sram page for indexed memory accesses in a multi-sram page psoc device. this register is only used when a device has more than one p age of sram. in the table above, note that reserved bits are grayed table cells and are not described in the bit descripti on section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 42 in the ram paging chapter . 2:0 page bits[2:0] bits determine which sram page an indexed memory access operates on. see the register defini- tions on page 42 for more information on when this register is active. 000b sram page 0 001b sram page 1 010b sram page 2 011b sram page 3 100b sram page 4 101b sram page 5 110b sram page 6 111b sram page 7 individual register names and addresses: 0,d3h idx_pp : 0,d3h 7 6 5 4 3 2 1 0 access : por rw : 0 bit name page bits[2:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 237 mvr_pp 0,d4h 21.3.49 mvr_pp mvi read page pointer register this register is used to set the effective sram page for mvi read memory accesses in a multi-sram page psoc device. this register is only used when a device has more than one p age of sram. in the table above, note that reserved bits are grayed table cells and are not described in the bit descripti on section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 42 in the ram paging chapter . 2:0 page bits[2:0] bits determine which sram page an mvi read instruction operates on. 000b sram page 0 001b sram page 1 010b sram page 2 011b sram page 3 100b sram page 4 101b sram page 5 110b sram page 6 111b sram page 7 individual register names and addresses: 0,d4h mvr_pp : 0,d4h 7 6 5 4 3 2 1 0 access : por rw : 0 bit name page bits[2:0] bit name description [+] feedback
238 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c mvw_pp 0,d5h 21.3.50 mvw_pp mvi write page pointer register this register is used to set the effective sram page for mvi write memory accesses in a multi-sram page psoc device. this register is only used when a device has more than one p age of sram. in the table above, note that reserved bits are grayed table cells and are not described in the bit descripti on section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 42 in the ram paging chapter . 2:0 page bits[2:0] bits determine which sram page an mvi write instruction operates on. 000b sram page 0 001b sram page 1 010b sram page 2 011b sram page 3 100b sram page 4 101b sram page 5 110b sram page 6 111b sram page 7 individual register names and addresses: 0,d5h mvw_pp : 0,d5h 7 6 5 4 3 2 1 0 access : por rw : 0 bit name page bits[2:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 239 i2c_cfg 0,d6h 21.3.51 i2c_cfg i 2 c configuration register this register is used to set the basic operating modes, baud rate, and interrupt selection. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. always write reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 122 in the i2c slave chapter . 6 p select i2c pin select. 0 p1[5] and p1[7]. 1 p1[0] and p1[1]. note read the i2c slave chapter for a discussion of the side effects of choosing the p1[0] and p1[1] pair of pins. 4stop ie stop interrupt enable. 0 disabled. 1 enabled. an interrupt is generated on the detection of a stop condition. 3:2 clock rate[1:0] 00b 100k standard mode. 01b 400k fast mode. 10b 50k standard mode. 11b reserved.. 0enable 0 disabled. 1 enabled. individual register names and addresses: 0,d6h i2c_cfg : 0,d6h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 bit name pselect stop ie clock rate[1:0] enable bit name description [+] feedback
240 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c i2c_scr 0,d7h 21.3.52 i2c_scr i 2 c status and control register this register is used by the slave to control the flow of data bytes and to keep track of the bus state during a transfer. bits in this register are held in reset until one of the enable bits in i2c_cfg is set. in the table above, note that the reser ved bit is a grayed table cell and not described in the bit descri ption section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 122 in the i2c slave chapter . 7 bus error 0 status bit. it must be cleared by firmware by writing a ?0? to the bit position. it is never cleared by the hardware. 1 a misplaced start or stop condition was detected. 5stop status 0 status bit. it must be cleared by firmware with a write of ?0? to the bit position. it is never cleared by the hardware. 1 a stop condition was detected. 4 ack acknowledge out. bit is automatically cleared by hardware upon a byte complete event. 0 nack the last received byte. 1 ack the last received byte 3 address 0 status bit. it must be cleared by firmware with a write of ?0? to the bit position. 1 the received byte is a slave address. 2transmit bit is set by firmware to define the direction of the byte transfer. any start detect or a write to the start or restart generate bits when operating in master mode also clears the bit. 0 receive mode. 1 transmit mode. 1lrb last received bit. the value of the 9 th bit in a transmit sequence, which is the acknowledge bit from the receiver. any start detect or a write to the start or restart generate bits when operating in master mode also clears the bit. 0 last transmitted byte was ack?ed by the receiver. 1 last transmitted byte was nack?ed by the receiver. 0byte complete transmit/receive mode: 0 no completed transmit/receive since last clear ed by firmware. any start detect or a write to the start or restart generate bits when oper ating in master mode also clears the bit. transmit mode: 1 eight bits of data have been transmitted and an ack or nack has been received. receive mode: 1 eight bits of data have been received. individual register names and addresses: 0,d7h i2c_scr : 0,d7h 7 6 5 4 3 2 1 0 access : por rc : 0 rc : 0 rw : 0 rc : 0 rw : 0 rc : 0 rc : 0 bit name bus error stop status ack address transmit lrb byte complete bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 241 i2c_dr 0,d8h 21.3.53 i2c_dr i 2 c data register this register provides read/write access to the shift register. this register is read only for received data and write only for transmitted data. for additional information, refer to the register definitions on page 122 in the i2c slave chapter . 7:0 data[7:0] read received data or write data to transmit. individual register names and addresses: 0,d8h i2c_dr : 0,d8h 7 6 5 4 3 2 1 0 access : por rw : 00 bit name data[7:0] bit name description [+] feedback
242 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c int_clr0 0,dah 21.3.54 int_clr0 interrupt clear register 0 this register enab les the individual interrupt sources? ability to clear po sted interrupts. when bits in this register are read, a ?1? is returned for ev ery bit position that has a corresponding posted interrupt. when b its in this register are written with a ?0? and enswint is not se t, posted interrupts are cleared at the corresponding bit position s. if there is no posted interrupt, there is no effect. when bits in this register are written with a ?1? and enswint is set, an i nter- rupt is posted in the interrupt controller . for additional information, refer to the register definitions on page 48 in the interrupt controller chapter. 7i2c read 0 no posted interrupt for i2c. read 1 posted interrupt present for i2c. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for i2c. 6 sleep read 0 no posted interrupt for sleep timer. read 1 posted interrupt present for sleep timer. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for sleep timer. 5 spi read 0 no posted interrupt for spi. read 1 posted interrupt present for spi. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for spi. 4gpio read 0 no posted interrupt for general purpose inputs and outputs (gpio) (pins). read 1 posted interrupt present for gpio (pins). write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for general purpose inputs and outputs (pins). (continued on next page) individual register names and addresses: 0,dah int_clr0 : 0,dah 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name i2c sleep spi gpio timer0 truetouch analog v monitor bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 243 int_clr0 0,dah 21.3.54 int_clr0 (continued) 3timer0 read 0 no posted interrupt for timer. read 1 posted interrupt present for timer. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for timer. 2 truetouch read 0 no posted interrupt for truetouch. read 1 posted interrupt present for truetouch. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for truetouch. 1analog read 0 no posted interrupt for analog. read 1 posted interrupt present for analog. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for analog. 0v monitor read 0 no posted interrupt for supply voltage monitor. read 1 posted interrupt present for supply voltage monitor. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for supply voltage monitor. [+] feedback
244 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c int_clr1 0,dbh 21.3.55 int_clr1 interrupt clear register 1 this register is used to enable the individual interrupt sources' ability to clear posted interrupts. when bits in this register are read, a '1' is returned for ev ery bit position that has a corresponding posted interrupt. when b its in this register are written with a '0' and enswint is not set, posted interrupts are cleared at the corresponding bit position s. if there is no posted interrupt, there is no effect. when bits in this register are written with a '1' and enswint is set, an i nter- rupt is posted in the interrupt controller. for additional information, refer to the register definitions on page 48 in the interrupt controller chapter. 7 endpoint3 read 0 no posted interrupt for usb endpoint3. read 1 posted interrupt present for usb endpoint3. write 0 and enswint = 0 clear pos ted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb endpoint3. 6 endpoint2 read 0 no posted interrupt for usb endpoint2. read 1 posted interrupt present for usb endpoint2. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb endpoint2. 5 endpoint1 read 0 no posted interrupt for usb endpoint1. read 1 posted interrupt present for usb endpoint1. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb endpoint1. (continued on next page) individual register names and addresses: 0,dbh int_clr1 : 0,dbh 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name endpoint3 endpoint2 endpoint1 endpoint0 usb_sof usb_bus_rst timer2 timer1 bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 245 int_clr1 0,dbh 21.3.55 int_clr1 ( continued ) 4 endpoint0 read 0 no posted interrupt for usb endpoint0. read 1 posted interrupt present for usb endpoint0. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb endpoint0. 3usb_sof read 0 no posted interrupt for usb start of frame (sof). read 1 posted interrupt present for usb start of frame (sof). write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb start of frame(sof). 2 usb_bus_rst read 0 no posted interrupt for usb bus reset. read 1 posted interrupt present for usb bus reset. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb bus reset. 1timer2 read 0 no posted interrupt for timer2. read 1 posted interrupt present for timer2. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for timer2. 0timer1 read 0 no posted interrupt for timer1 read 1 posted interrupt present for timer1. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for timer1. [+] feedback
246 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c int_clr2 0,dch 21.3.56 int_clr2 interrupt clear register 2 this register is used to enable the individual interrupt sources' ability to clear posted interrupts. when bits in this register are read, a '1' is returned for ev ery bit position that has a corresponding posted interrupt. when b its in this register are written with a '0' and enswint is not set, posted interrupts are cleared at the corresponding bit position s. if there is no posted interrupt, there is no effect. in the tabl e above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must al ways be written with a value of ?0?. when bits in this reg - ister are written with a '1' and enswint is set, an interrupt is posted in the interrupt controller. for additional information , refer to the register definitions on page 48 in the interrupt controller chapter. 5 usb_wake read 0 no posted interrupt for usb wake. read 1 posted interrupt present for usb wake. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb wake. 4 endpoint8 read 0 no posted interrupt for usb endpoint8. read 1 posted interrupt present for usb endpoint8. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb endpoint8. (continued on next page) individual register names and addresses: 0,dch int_clr2 : 0,dch 7 6 5 4 3 2 1 0 access : rw:00 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name usb_wake endpoint8 endpoint7 endpoint6 endpoint5 endpoint4 bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 247 int_clr2 0,dch 21.3.56 int_clr2 ( continued ) 3 endpoint7 read 0 no posted interrupt for usb endpoint7. read 1 posted interrupt present for usb endpoint7. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb endpoint7. 2 endpoint6 r ead 0 no posted interrupt for usb endpoint6. read 1 posted interrupt present for usb endpoint6. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb endpoint6. 1 endpoint5 read 0 no posted interrupt for usb endpoint5. read 1 posted interrupt present for usb endpoint5. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb endpoint5 0 endpoint4 read 0 no posted interrupt for usb endpoint4. read 1 posted interrupt present for usb endpoint4. write 0 and enswint = 0 clear posted interrupt if it exists. write 1 and enswint = 0 no effect. write 0 and enswint = 1 no effect. write 1 and enswint = 1 post an interrupt for usb endpoint4. [+] feedback
248 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c int_msk2 0,deh 21.3.57 int_msk2 interrupt mask register 2 this register enables the individual sources' ability to create pending interrupts. when an interrupt is masked off, the mask bit is '0'. the interrupt continues to post in the interrupt controller. clearing the mask bit only prevents a posted interrupt from becoming a pending interrupt. in the table above, note that reserved bits are grayed table cells and are not described in the bit descripti on section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 48 in the interrupt controller chapter. 5 usb wakeup 0 mask usb wakeup interrupt. 1 unmask usb wakeup interrup. 4 endpoint8 0 mask usb endpoint8 interrupt. 1 unmask usb endpoint8 interrupt. 3 endpoint7 0 mask usb endpoint7 interrupt. 1 unmask usb endpoint7 interrupt. 2 endpoint6 0 mask usb endpoint6 interrupt. 1 unmask usb endpoint6 interrupt. 1 endpoint5 0 mask usb endpoint5 interrupt. 1 unmask usb endpoint5 interrupt. 0 endpoint4 0 mask usb endpoint4 interrupt. 1 unmask usb endpoint4 interrupt. individual register names and addresses: 0,deh int_msk2 : 0,deh 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name usb wakeup endpoint8 endpoint7 endpoint6 endpoint5 endpoint4 bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 249 int_msk1 0,dfh 21.3.58 int_msk1 interrupt mask register 1 this register enables the individual sources' ability to create pending interrupts. when an interrupt is masked off, the mask bit is '0'. the interr upt continues to post in the interrupt controller. clearing the mask bit only prevents a posted interrupt from becoming a pending interrupt. for additional information, refer to the register definitions on page 48 in the interrupt controller chapter. 7 endpoint3 0 mask usb endpoint3 interrupt. 1 unmask usb endpoint3 interrupt. 6 endpoint2 0 mask usb endpoint2 interrupt. 1 unmask usb endpoint2 interrupt. 5 endpoint1 0 mask usb endpoint1 interrupt. 1 unmask usb endpoint1 interrupt. 4 endpoint0 0 mask usb endpoint0 interrupt. 1 unmask usb endpoint0 interrupt. 3 usb sof 0 mask usb sof interrupt. 1 unmask usb sof interrupt. 2 usb bus reset 0 mask usb bus reset interrupt. 1 unmask usb bus reset interrupt. 1timer2 0 mask timer2 interrupt. 1 unmask timer2 interrupt. 0timer1 0 mask timer1 interrupt. 1 unmask timer1 interrupt. individual register names and addresses: 0,dfh int_msk1 : 0,dfh 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name endpoint3 endpoint2 endpoint1 endpoint0 usb sof usb bus reset timer2 timer1 bit name description [+] feedback
250 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c int_msk0 0,e0h 21.3.59 int_msk0 interrupt mask register 0 this register enables the individual sources? ability to create pending interrupts. when an interrupt is masked off, the mask bit is ?0?. the interrupt continues to post in the interrupt controller. clearing the mask bit only prevents a posted interrupt from becoming a pending interrupt. for additional information, refer to the register definitions on page 48 in the interrupt controller chapter. 7i2c 0 mask i2c interrupt. 1 unmask i2c interrupt. 6 sleep 0 mask sleep interrupt. 1 unmask sleep interrupt. 5 spi 0 mask spi interrupt. 1 unmask spi interrupt. 4gpio 0 mask gpio interrupt. 1 unmask gpio interrupt. 3timer0 0 mask timer0 interrupt. 1 unmask timer0 interrupt. 2 truetouch 0 mask truetouch interrupt. 1 unmask truetouch interrupt. 1analog 0 mask analog interrupt. 1 unmask analog interrupt. 0v monitor 0 mask voltage monitor interrupt. 1 unmask voltage monitor interrupt. individual register names and addresses: 0,e0h int_msk0 : 0,e0h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name i2c sleep spi gpio timer0 truetouch analog v monitor bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 251 int_sw_en 0,e1h 21.3.60 int_sw_en interrupt software enable register this register is used to enable software interrupts. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 48 in the interrupt controller chapter. 0 enswint 0 disable software interrupts. 1 enable software interrupts. individual register names and addresses: 0,e1h int_sw_en : 0,e1h 7 6 5 4 3 2 1 0 access : por rw : 0 bit name enswint bit name description [+] feedback
252 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c int_vc 0,e2h 21.3.61 int_vc interrupt vector clear register this register returns the next pending interrupt and clears all pending interrupts when written. for additional information, refer to the register definitions on page 48 in the interrupt controller chapter. 7:0 pending interrupt[7:0] read returns vector for highest priority pending interrupt. write clears all pending and posted interrupts. individual register names and addresses: 0,e2h int_vc : 0,e2h 7 6 5 4 3 2 1 0 access : por rc : 00 bit name pending interrupt[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 253 res_wdt 0,e3h 21.3.62 res_wdt reset watchdog timer register this register is used to clear the watchdog timer alone, or clear both the watchdog timer and the sleep timer together. for additional information, refer to the register definitions on page 77 in the sleep and watchdog chapter. 7:0 wdsl_clear[7:0] any write clears the watchdog timer. a write of 38h clears both the watchdog and sleep timers. individual register names and addresses: 0,e3h res_wdt : 0,e3h 7 6 5 4 3 2 1 0 access : por w : 00 bit name wdsl_clear[7:0] bit name description [+] feedback
254 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cpu_f x,f7h 21.3.63 cpu_f m8c flag register this register provides read access to the m8c flags. the and f, expr; or f, expr; and xor f, expr flag instructions are used to modify this register. in the table above, note that the reserved bit is a grayed table cell and is not described in th e bit description section below. reserved bits must always be wri t- ten with a value of ?0?. for additional information, refer to the register definitions on page 32 in the m8c chapter and the reg- ister definitions on page 48 in the interrupt controller chapter. 7:6 pgmode[1:0] 00b direct address mode and indexed address mode operands are referred to ram page 0, regardless of the values of cur_pp and idx_ pp. note that this condition prevails upon entry to an interrupt service routine when the cpu_f register is cleared. 01b direct address mode instructions are referred to page 0. indexed address mode instructions are referr ed to the ram page specified by the stack page pointer, stk_pp. 10b direct address mode instructions are refe rred to the ram page specified by the current page pointer, cur_pp. indexed address mode instructi ons are referred to the ram page specified by the index page pointer, idx_pp. 11b direct address mode instructions are refe rred to the ram page specified by the current page pointer, cur_pp. indexed address mode instructions are referr ed to the ram page specified by the stack page pointer, stk_pp. 5binc bit implemented not connected. 4xio 0 normal register address space. 1 extended register address space. primarily used for configuration. 2 carry set by the m8c cpu core to indicate whether t here has been a carry in the previous logical/arith- metic operation. 0no carry. 1carry. (continued on next page) individual register names and addresses: x,f7h cpu_f : x,f7h 7 6 5 4 3 2 1 0 access : por rl : 0 rl : 0 rl : 0 rl : 0 rl : 0 rl : 0 bit name pgmode[1:0] binc xio carry zero gie bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 255 cpu_f x,f7h 21.3.63 cpu_f (continued) 1zero set by the m8c cpu core to indicate whether there was a zero result in the previous logical/arith- metic operation. 0 not equal to zero. 1 equal to zero. 0gie 0 m8c does not process any interrupts. 1 interrupt processing enabled. [+] feedback
256 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c idac_d 0,fdh 21.3.64 idac_d current dac data register this register specifies the 8-bit multiplying fa ctor that determines the output idac current. for additional information, refer to the register definitions on page 92 in the truetouch module chapter. 7:0 idacdata[7:0] this is an 8-bit value that selects the number of cu rrent units that combine to form the idac current. this current then drives the analog mux bus when idac mode is enabled. for example, a setting of 80h means that the charging current is 128 current units. the current size also depends on the irange setting in the cs_cr2 register. this setting supplies the charging current for the relaxation oscillator. this current and the external capacitance connected to the analog global bus determines the ro frequency. this register is also used to set the c harging current in the proximity detect mode. step size is approximately 330 na/bit for default irange state 00b. 00h smallest current. . . . ffh largest current. individual register names and addresses: 0,fdh idac_d : 0,fdh 7 6 5 4 3 2 1 0 access : por rw : 00 bit name idacdata[7:0] bits name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 257 cpu_scr1 x,feh 21.3.65 cpu_scr1 system status and control register 1 this register is used to convey the status and control of events related to internal resets and watchdog reset. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 137 in the system resets chapter. 7 iress this bit is read only. 0 boot phase only executed once. 1 boot phase occurred multiple times. 4:3 slimo[1:0] these bits set the frequency range for the imo. note when changing from the default setting, the corresponding trim value must be loaded into the imo_tr register for highest frequency accuracy. slimo cy8ctmg20x/ cy8ctst200 00 12 01 6 10 24 11 reserved 0 iramdis 0 sram is initialized to 00h after por, xres, and wdr. 1 addresses 03h - d7h of sram page 0 are not modified by wdr. individual register names and addresses: x,feh cpu_scr1: x,feh 7 6 5 4 3 2 1 0 access : por r : 0 rw : 0 rw : 0 bit name iress slimo[1:0] iramdis bit name description [+] feedback
258 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c cpu_scr0 x,ffh 21.3.66 cpu_scr0 system status and control register 0 this register is used to convey the status and cont rol of events for various functions of a psoc device. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 137 in the system resets chapter. 7gies global interrupt enable status. it is recommended that the user read the global interrupt enable flag bit from the cpu_f register on page 254 . this bit is read only for gies . its use is discouraged, as the flag register is now readable at address x,f7h (read only). 5 wdrs watchdog reset status. this bit may not be set by us er code; however, it may be cleared by writing a ?0?. 0 no watchdog reset has occurred. 1 watchdog reset has occurred. 4pors power on reset status. this bit may not be set by user code; however, it may be cleared by writing a ?0?. 0 power on reset has not occurred and watchdog timer is enabled. 1 is set after external reset or power on reset. 3 sleep set by the user to enable the cpu sleep state. cpu remains in sleep mode until any interrupt is pending. 0 normal operation. 1sleep. 0stop 0 m8c is free to execute code. 1 m8c is halted and is only clear ed by por, xres, or wdr. individual register names and addresses: x,ffh cpu_scr0 : x,ffh 7 6 5 4 3 2 1 0 access : por r : 0 rc : 0 rc : 1 rw : 0 rw : 0 bit name gies wdrs pors sleep stop bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 259 prtxdm0 1,00h 21.4 bank 1 registers the following registers are all in bank 1 and are listed in addr ess order. registers that are in both bank 0 and bank 1 are listed in address order in the section titled bank 0 registers on page 188 . 21.4.1 prtxdm0 port drive mode bit registers 0 this register is one of two registers where the combined val ue determines the unique drive mode of each bit in a gpio port. in register prtxdm0 there are four possible drive modes for eac h port pin. two mode bits are required to select one of these modes, and these two bits are spread into two different registers (prtxdm0 and prtxdm1 on page 260 ). the bit position of the effected port pin (for example, pin[2] in port 0) is the sa me as the bit position of each of the two drive mode register bi ts that control the drive mode for that pin (for example, bit[2] in prt0dm0 and bit[2] in prt0dm1). the two bits from the two registers are treated as a group. these are referred to as dm1 and dm0, or together as dm[1:0]. all drive mode bits are shown in the sub-table below ([1 0 ] refers to the combination (in order) of bits in a given bit position); however, this register only controls the least significant bit (lsb) of the drive mode. the upper nibble of the prt4dm0 register returns the last data bus value when read. you need to mask it off prior to using this information. for additional information, refer to the register definitions on page 59 in the gpio chapter. 7:0 drive mode 0[7:0] bit 0 of the drive mode, for each of 8-port pins, for a gpio port. [ 1 0] pin output high pin output low notes 0 0 bresistive strong 0 1 b strong strong 1 0 b high z high z reset state. digita l input disabled for zero power. 1 1 b high z strong i2c compatible mode. for digital inputs, use this mode with data bit (prtxdr register) set high. note a bold digit in the table above signifies t hat the digit is used in this register. individual register names and addresses: 1,00h prt0dm0 : 1,00h prt1dm0 : 1,04h prt2dm0 : 1,08h prt3dm0 : 1,0ch prt4dm0 : 1,10h 7 6 5 4 3 2 1 0 access : por rw : 00 bit name drive mode 0[7:0] bit name description [+] feedback
260 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c prtxdm1 1,01h 21.4.2 prtxdm1 port drive mode bit registers 1 this register is one of three registers where the combined value determines the unique drive mode of each bit in a gpio port. in register prtxdm1 there are four possibl e drive modes for each port pin. two mode bi ts are required to select one of these modes, and these two bits are spread into two different registers (prtxdm1 and prtxdm0 on page 259 ). the bit position of the effected port pin (for example, pin[2] in port 0) is the sa me as the bit position of each of the two drive mode register bi ts that control the drive mode for that pin (for example, bit[2] in prt0dm0 and bit[2] in prt0dm1). the two bits from the two registers are treated as a group. these are referred to as dm1 and dm0, or together as dm[1:0]. all drive mode bits are shown in the sub-table below ([ 1 0] refers to the combination (in order) of bits in a given bit position); however, this register only controls the most significant bit (msb) of the drive mode. the upper nibble of the prt4dm1 register returns the last data bus value when read. you need to mask it off before using this information. for additional information, refer to the register definitions on page 59 in the gpio chapter. 7:0 drive mode 1[7:0] bit 1 of the drive mode, for each of 8-port pins, for a gpio port. [1 0 ] pin output high pin output low notes 0 0b resistive strong 0 1b strong strong 1 0b high z high z reset state. digita l input disabled for zero power. 1 1b high z strong i2c compatible mode. for digital inputs, use this mode with data bit (prtxdr register) set high. note a bold digit in the table above signifies t hat the digit is used in this register. individual register names and addresses: 1,01h prt0dm1 : 1,01h prt1dm1 : 1,05h prt2dm1 : 1,09h prt3dm1 : 1,0dh prt4dm1 : 1,11h 7 6 5 4 3 2 1 0 access : por rw : ff bit name drive mode 1[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 261 spi_cfg 1,29h 21.4.3 spi_cfg spi configuration register this register is used to configure the spi. do not change the values in this register while the block is enabled. for additional information, refer to the register defini- tions on page 147 in the spi chapter. 7:5 clock sel [2:0] sysclk in master mode. 000b / 2 001b / 4 010b / 8 011b / 16 100b / 32 101b / 64 110b / 128 111b / 256 4 bypass bypass synchronization. 0 all pin inputs are doubled and synchronized. 1 input synchronization is bypassed. 3 ss_ slave select in slave mode. 0 slave selected. 1 slave not selected. 2 ss_en_ internal slave select enable. 0 slave selection determined from ss_ bit. 1 slave selection determined from external ss_ pin. 1int sel interrupt select. 0 interrupt on tx reg empty. 1 interrupt on spi complete. 0 slave 0 operates as a master. 1 operates as a slave. individual register names and addresses: 1,29h spi_cfg : 1,29h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name clock sel [2:0] bypass ss_ ss_en_ int sel slave bit name description [+] feedback
262 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c usb_cr1 1,30h 21.4.4 usb_cr1 usb control register 1 this register is used to configure the internal regulator and the oscillator tuning capability. this register is only used by the cy8ctmg20x, cy8ctst200 pso c devices. in the table above, note that reserved bits are grayed table cells and are not described in the bit descripti on section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 2busactivity monitors activity on usb bus. this bit is only set by the hardware. wr iting a ?0? clears this bit. writing a ?1? preserves its present state. 0 no activity. 1 non-idle activity (d+ = low) was detect ed since the last time the bit was cleared. 1 enablelock controls the automatic tuning of t he internal oscillator. hardware lo cks the internal oscillator based on the frequency of incoming usb data when this bit is se t. normally, this is se t when the device is used in a usb application. 0 locking disabled. 1 locking enabled. 0 regenable configures usb regulator for appropriate power supply range. 0 pass through mode. use for vdd = 3.3v range. 1 regulating mode. use for vdd = 5v range. individual register names and addresses: 1,30h usb_cr1 : 1,30h 7 6 5 4 3 2 1 0 access : por rc : 0 rw : 0 rw : 0 bit name busactivity enablelock regenable bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 263 pmax_wa 1,34h 21.4.5 pmax_wa psoc memory arbiter wr ite address registers these registers are psoc memory arbiter write address registers. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7:0 write address[7:0] the value returned when this register is r ead depends on whether the pma channel is being used by the usb sie or by the m8c. individual register names and addresses: 1,34h pma0_wa : 1,34h pma1_wa : 1,35h pma2_wa : 1,36h pma3_wa : 1,37h pma4_wa : 1,38h pma5_wa : 1,39h pma6_wa : 1,3ah pma7_wa : 1,3bh pma8_wa : 1,44h pma9_wa : 1,45h pma10_wa : 1,46h pma11_wa : 1,47h pma12_w a : 1, 48h pma13_wa : 1,49h pma14_wa : 1,4ah pma15_wa : 1,4bh 7 6 5 4 3 2 1 0 access : por rw : 00 bit name write address[7:0] bit name description [+] feedback
264 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c pmax_ra 1,3ch 21.4.6 pmax_ra psoc memory arbiter read address registers these registers are psoc memory ar biter read address registers. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7:0 readaddress[7:0] the value returned when this register is re ad depends on whether the pma channel is being used by the usb sie or by the m8c. in the usb case, this register always returns the beginning sram address for the pma channel. individual register names and addresses: 1,3ch pma0_ra : 1,3ch pma1_ra : 1,3dh pma2_ra : 1,3eh pma3_ra : 1,3fh pma4_ra : 1,40h pma5_ra : 1,41h pma6_ra : 1,42h pma7_ra : 1,43h pma8_ra : 1,4ch pma9_ra : 1,4dh pma10_ra : 1,4eh pma11_ra : 1,4fh pma12_ra : 1, 50h pma13_ra : 1,51h pma14_ra : 1,52h pma15_ra : 1,53h 7 6 5 4 3 2 1 0 access : por rw : 00 bit name read address[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 265 epx_cr0 1,54h 21.4.7 epx_cr0 endpoint control registers 0 these registers endpoint control registers. in the table above, note that the reserved bit is a grayed table cell and is not described in the bit description section below . reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 171 in the full-speed usb chapter. 7stall when this bit is set, the sie stalls an out packet if the mode bits are set to ack-out. the sie stalls an in packet if the mode bits are set to ack- in. this bit must be clear for all other modes. 5 nak_int_en when set, this bit causes an endpoint interrupt to be generated even when a transfer completes with a nak. 4 acked tx the ack'ed transaction bit is set whenever the si e engages in a transaction to the register's end- point that completes with an ack packet. 3:0 mode[3:0] the mode controls how the usb sie responds to traffic and how the usb sie changes the mode of that endpoint as a result of host packets to the endpoint. individual register names and addresses: 1,54h ep1_cr0 : 1,54h ep2_cr0 : 1,55h ep3_cr0 : 1,56h ep4_cr0 : 1,57h ep5_cr0 : 1,58h ep6_cr0 : 1,59h ep7_cr0 : 1,5ah ep7_cr0 : 1,5bh 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rc : 0 rw : 0 bit name stall nak_int_en ack?ed tx mode[3:0] bit name description [+] feedback
266 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c tmp_drx x,6ch 21.4.8 tmp_drx temporary data registers these registers enhance the performance in multiple sram page psoc devices. all bits in this register are reserved for psoc devices with 256 bytes of sram. for additional information, refer to the register definitions on page 42 in the ram paging chapter . 7:0 data[7:0] general purpose register space individual register names and addresses: x,6ch tmp_dr0 : x,6ch tmp_dr1 : x,6dh tmp_dr2 : x,6eh tmp_dr3 : x,6fh 7 6 5 4 3 2 1 0 access : por rw : 00 bit name data[7:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 267 usb_misc_cr 1,bdh 21.4.9 usb_misc_cr usb miscellaneous control register the usb miscellaneous control register controls the clocks to the usb block to make imo work with better accuracy for the usb part and to disable the single ended input of usbio in the case of a non-usb part. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 112 in the digital clocks chapter. 2 use_se_en the single ended outputs of usbio is enabled or dis abled based upon this bit setting. set this bit to '1' when using this part as a usb part. 0 the single ended ouputs of usbio are disabled. the dpo, dmo is held at logic high state and rseo is held at a low state. 1 the single ended output of usbio is enabled and usb transactions can occur. note bit [1:0] of the usbio_cr1 register is also affe cted by this register setti ng. when this bit is '0' (default) regardless of the dp and dm state, the dpo and dmo bits of usbio_cr1 are '11b'. 1usb_on this bit is used by the imo dac block to either work with better dnl consuming higher power, or with sacrificed dnl consuming lower power. set this bi t to '1' when the part is used as a usb part. 0 the imo runs with sacrificed dnl by consuming less power. 1 the imo runs with better dnl by consuming more power. 0 usb_clk_on this bit either enables or disables the clocks to t he usb block. it is used to save power in cases when the device need not respond to usb traffic. set this bit to '1' when the device is used as a usb part. 0 all clocks to the usb block are driven as '0'. the device does not respond to usb traffic and none of the usb registers, except imo_tr, imo_tr1 and usbio_cr1, listed in the regis- ter definitions on page 171 are writable. 1 clocks are not blocked to the usb block. the device responds to usb traffic depending upon the other register settings mentioned in register definitions on page 171 in the full- speed usb chapter. individual register names and addresses: 1,bdh usb_misc_cr: 1,bdh 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name usb_se_en usb_on usb_clk_on bit name description [+] feedback
268 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c out_p0 1,d1h 21.4.10 out_p0 output override to port 0 register this register enables specific internal signals to output to port 0 pins. the gpio drive modes must be specified to support the desir ed output mode (registers prt1dm1 and prt1dm0). if a pin is enabled for output by a bit in this register, the corresponding si gnal has priority over any other internal function that may b e configured to output to that pin. for additional information, refer to the register definitions on page 112 in the digital clocks chapter. 7 p0p7d 0 select main system clock (sysclk). 1 select either truetouch output signal (c s_out is selected by cs_out[1:0] bits in cs_cr0 register) or truetouch clock depending upon bit 7 in prs_cr register. 6 p0p7en this bit enables pin p0 [7] for output of the signal selected by p0p7d. 0 no internal signal output to p0 [7]. 1 output the signal selected by p0p7d on to p0[7]. 5 p0p4d 0 select timer output (timerout) 1select clk32 note : during sleep mode these outputs will not be passed through p0[4]. 4 p0p4en this bit enables pin p0 [4] for output of the signal selected by p0p4d. 0 no internal signal output to p0 [4]. 1 output the signal selected by p0p4d on to p0[4]. individual register names and addresses: 1,d1h out_p0: 1,d1h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 bit name p0p7d p0p7en p0p4d p0p4en bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 269 eco_enbus 1,d2h 21.4.11 eco_enbus external oscillat or enbus register the eco_enbus register is used to disable and enable the external crystal oscillator (eco). in the table above, note that reserved bits are grayed table cells and are not described in th e bit description section. reserved bits should always be writ- ten with a value of ?0?. see the application overview on page 70 for the proper sequence for enabling the eco. 2:0 eco_enbus[2:0] these bits should be written with a value of 011b to allow the ec o to be enabled by bits in the eco_cfg register, or a value of 111b (default) to di sable the eco. other values in this register are reserved. individual register names and addresses: 1,d2h eco_enbus : 1,d2h 7 6 5 4 3 2 1 0 access : por rw : 7 bit name eco_enbus[2:0] bits name description [+] feedback
270 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c eco_trim 1,d3h 21.4.12 eco_trim external oscillator trim register this register trims the external oscillator gain and power settings. these settings in this register should not be changed from their default state. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 100 in the i/o analog multiplexer chapter. 4:2 eco_xgm[2:0] these bits set the amplifier gain. the high power mode setup size is approximately 220 na. the low power step size is approxima tely 5% lower than the 111 setting. 000 lowest power setting. 111 highest power setting. 1:0 eco_lp[1:0] these regulate low power mode settings. 00 highest power setting. 11 lowest power setting (30% power reduction). individual register names and addresses: 1,d3h eco_trim : 1,d3h 7 6 5 4 3 2 1 0 access : por rw : 4 rw : 1 bit name eco_xgm[2:0] eco_lp[1:0] bits name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 271 mux_crx 1,d8h 21.4.13 mux_crx analog mux port bit enable registers this register is used to control the connection between the analog mux bus and the corresponding pin. port 4 is a 4-bit port, so the upper 4 bits of the mu x_cr4 register are reserved and return zeros when read. for additional information, refer to the register definitions on page 100 in the i/o analog multiplexer chapter. 7:0 enable[7:0] each bit controls the connection between the an alog mux bus and the corresponding port pin. for example, mux_cr2[3] controls the connection to bi t 3 in port 2. any number of pins may be con- nected at the same time. 0 no connection between port pin and analog mux bus. 1 connect port pin to analog mux bus. individual register names and addresses: 1,d8h mux_cr0 : 1,d8h mux_cr1 : 1,d9h mux_cr2 : 1,dah mux_cr3 : 1,dbh mux_cr4 : 1,dfh 7 6 5 4 3 2 1 0 access : por rw : 00 bit name enable[7:0] bits name description [+] feedback
272 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c io_cfg1 1,dch 21.4.14 io_cfg1 input/output configur ation register 1 this register is used to configure the port 1 output regulator and set the interrupt mode for all gpio. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 59 in the gpio chapter. 7 strongp setting this bit increases the drive strength and edge ratio for high outputs. 5:4 range[1:0] selects the high output level for port 1 outputs. 00 3.0 volts 01 3.0 volts 10 1.8 volts 11 2.5 volts 3 p1-low_thrs this bit reduces the threshold voltage of the p1 por t input buffers so that there are no compatibility issues when port 1 is communicating at regulated voltage levels. 0 standard threshold of vih, vil 1 reduce threshold of vih, vil 2 spiclk_on_p10 when set to ?1?, the spi clock is mapped to port 1 pin 0. otherwise, it is mapped to port 1 pin 3. 1reg_en controls the regulator on port 1 outputs. 0 regulator disabled, so port 1 strong outputs drive to vdd. 1 regulator enabled, so port 1 strong outputs drive to approximately 3v (for vdd > 3v). 0io int sets the gpio interrupt mode for all pins in the psoc device. gpio interrupts are also controlled at each pin by the prtxie registers, and by the global gpio bit in the int_msk0 register. 0 gpio interrupt configured for interrupt when pin is low. 1 gpio interrupt configured for interrupt when pin state changes from last time port was read. individual register names and addresses: 1,dch io_cfg1 : 1,dch 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name strongp range[1:0] p1_low_ thrs spiclk_ on_p10 reg_en io int bits name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 273 out_p1 1,ddh 21.4.15 out_p1 output override to port 1 register this register enables specific internal signals to be output to port 1 pins. the gpio drive modes must be specified to support the desir ed output mode (registers prt1dm1 and prt1dm0). if a pin is enabled for output by a bit in this register, the corresponding si gnal has priority over any other internal function that may b e configured to output to that pin. for additional information, refer to the register definitions on page 112 in the digital clocks chapter. 7 p16d bit selects the data output to p1[6] when p16en is high. timer output and clk32 are available on p0[4] as well, but outputs on p0[4] will not be pa ssed through during sleep modes. please refer to the out_p0 register for more details. 0 select timer output (timerout) 1select clk32 6 p16en bit enables pin p1[6] for output of the signal selected by the p16d bit. 0 no internal signal output to p1[6] 1 output the signal selected by p16d to p1[6] 5 p14d bit selects the data output to p1[4] when p14en is high. 0 select relaxation oscillator (ro) 1 select comparator 1 output (cmp1) 4 p14en bit enables pin p1[4] for output of the signal selected by the p14d bit. 0 no internal signal output to p1[4] 1 output the signal selected by p14d to p1[4] 3 p12d bit selects the data output to p1[2] when p12en is high. 0 select main system clock (sysclk) 1 select either truetouch output signal (c s_out is selected by cs_out[1:0] bits in cs_cr0 register) or truetouch clock depending upon bit 7 in prs_cr register. 2 p12en bit enables pin p1[2] for output of the signal selected by the p12d bit. 0 no internal signal output to p1[2] 1 output the signal selected by p12d to p1[2] (continued on next page) individual register names and addresses: 1,ddh out_p1: 1,ddh 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 rw : 0 bit name p16d p16en p14d p14en p12d p12en p10d p10en bit name description [+] feedback
274 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c out_p1 1,ddh 21.4.15 out_p1 (continued) 1 p10d bit selects the data output to p1[0] when p10en is high. 0 select sleep interrupt (slpint) 1 select comparator 0 output (cmp0) 0 p10en bit enables pin p1[0] for output of the signal selected by the p10d bit. 0 no internal signal output to p1[0] 1 output the signal selected by p10d to p1[0] [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 275 io_cfg2 1,deh 21.4.16 io_cfg2 input/output configur ation register 2 the input/output configuration 2 register (io_cfg2) selects output regulated supply and clock rates. in the table above, note that reserved bits are grayed table cell s and are not described in the bit description section. reserv ed bits should always be written with a value of ?0?. for additional information, refer to the io_cfg2 register on page 61 in the gpio chapter. 5:3 reg_level[2:0] these bits select output regulated supply 1:0 reg_clock[1:0] the regulated i/o charge pump can operate with a maximum clock speed of 12 mhz. the reg_clock[1:0] bits select clocking options fo r the regulator. setting reg_clock[1:0] to ?10? should be used with 24 mhz sysclk and ? 01? should be used with 6/12 mhz sysclk. individual register names and addresses: 1,deh io_cfg2 : 1,deh 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 bit name reg_level[2:0] reg_clock[1:0] bits name description reg_level[2:0] approx. regulated supply (v) 000 3 2.5 1.8 001 3.1 2.6 1.9 010 3.2 2.7 2.0 011 3.3 2.8 2.1 100 3.4 2.9 2.2 101 3.5 3.0 2.3 110 3.6 3.1 2.4 111 3.7 3.2 2.5 reg_clock[1:0] sysclk clock rate 10 24 mhz 01 6/12 mhz [+] feedback
276 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c osc_cr0 1,e0h 21.4.17 osc_cr0 oscillator control register 0 this register is used to configure various feat ures of internal clock sources and clock nets. in the table above, note that the reserved bit is a grayed table cell and is not described in the bit description section below . reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 112 in the digital clocks chapter. 7 x32on select bit for the external 32 khz external crystal oscillator (eco). see the application overview on page 70 for the proper sequence for enabling the eco. 0 the internal 32 khz oscillator is the source of the 32k clock. 1 the external crystal oscillator is the source of the 32k clock. 6 disable buzz option to disable buzz during sleep. this bit has lowe r priority than the no buzz bit. therefore, if no buzz = 1, the disable buzz bit has no effect. 0 no effect on buzz modes. 1 buzz is disabled during sleep, with b andgap powered down. no periodic wakeup of the bandgap during sleep. 5no buzz this bit allows the bandgap to stay powered during sleep. 0 buzz bandgap during power down. 1 bandgap is always powered even during sleep. 4:3 sleep[1:0] sleep interval. 00b 1.95 ms (512 hz) 01b 15.6 ms (64 hz) 10b 125 ms (8 hz) 11b 1s (1 hz) 2:0 cpu speed[2:0] these bits set the cpu clock speed, based on th e system clock (sysclk). sysclk is 12 mhz by default, but it can also be set to other frequencies (6 and 24 mhz), or driven from an external clock. note during usb operation, the cpu speed can be se t to any setting. be aware that usb through- put decreases with a decrease in cpu speed. for maximum throughput, the cpu clock should be made equal to the system clock. the sys tem clock must be 24 mhz for usb operation. 6 mhz imo 12 mhz imo 24 mhz imo external clock 000b 750 khz 1.5 mhz 3 mhz extclk/8 001b 1.5 mhz 3 mhz 6 mhz extclk/4 010b 3 mhz 6 mhz 12 mhz extclk/2 (reset state) 011b 6 mhz 12 mhz 24 mhz extclk/1 100b 375 khz 750 khz 1.5 mhz extclk/16 101b 187.5 khz 375 khz 750 khz extclk/32 110b 46.9 khz 93.7 khz 187.5 khz extclk/128 111b 23.4 khz 46.8 khz 93.7 khz extclk/256 individual register names and addresses: 1,e0h osc_cr0: 1,e0h 7 6 5 4 3 2 1 0 access : por rw: 0 rw : 0 rw : 0 rw : 0 rw : 010b bit name x32on disable buzz no buzz sleep[1:0] cpu speed[2:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 277 eco_cfg 1,e1h 21.4.18 eco_cfg external oscillator trim configuration register this register provides eco status and control information. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the eco_cfg register on page 71 in the external crystal oscillator chapter. 2eco_lpm this bit enables the eco lower power mode. 1eco_exw this is a status bit that indicates that the eco_ex bit was previously written to. when this bit is a '1', this indicates that the ec o_config register was written to and is now locked. when this bit is a '0', the register was not written to since the last reset event. 0eco_ex the eco exists bit is a flag to t he hardware indicating that an external crystal oscillator exists in the system.if the bit is '0', a switch-over to the eco is locked out by hardware. if the bit is '1', hardware allows the firmware to freely switch between the ec o and ilo. it must be written as early as possible after a power on reset (por) or external reset (xres) event. individual register names and addresses: 1,e1h eco_cfg : 1,e1h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name eco_lpm eco_exw eco_ex bits name description [+] feedback
278 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c osc_cr2 1,e2h 21.4.19 osc_cr2 oscillator control register 2 this register is used to configure various feat ures of internal clock sources and clock nets. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 112 in the digital clocks chapter. 4 clk48men this is the 48 mhz clock enable bit. 0 disables the 48 mhz clock. 1 enables the 48 mhz clock. 2 extclken external clock mode enable. 0 disabled. operate from in ternal main oscillator. 1 enabled. operate from the cl ock supplied at p1[4] or p1[1] based upon the tsync bit in cpu_scr1. 1imodis internal oscillator disable. this bit can be set to save power when using an external clock on p1[4]. 0 enabled. internal oscillator enabled. 1 disabled. note this bit must not be set high in the same inst ruction that sets extclken high, but it can be set in the next instruction. also, this bit must not be set high if the external clock frequency is less than 6 mhz. when switching from external clock to internal clock, the imo must be enabled for at least 10 s before the transition to internal clock. refer to switch operation on page 110 . individual register names and addresses: 1,e2h osc_cr2 : 1,e2h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name clk48men extclken imodis bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 279 vlt_cr 1,e3h 21.4.20 vlt_cr voltage monitor c ontrol register this register is used to set the trip points for por and lvd. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 144 in the por chapter. 5:4 porlev[1:0] sets the por level according to the dc electric al specifications in the psoc device data sheet. 3 lvdtben enables reset of the cpu speed register by lvd comparator output. 2:0 vm[2:0] sets the lvd levels per the dc electrical specif ications in the psocdev ice data sheet, for those devices with this feature. 000b lowest voltage setting. 001b 010b 011b 100b 101b 110b 111b highest voltage setting. individual register names and addresses: 1,e3h vlt_cr: 1,e3h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name porlev[1:0] lvdtben vm[2:0] bit name description [+] feedback
280 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c vlt_cmp 1,e4h 21.4.21 vlt_cmp voltage monitor comparators register this register reads the state of the internal supply voltage monitors. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 144 in the por chapter. 1lvd this bit reads the state of the lvd comparator. 0 vdd is above lvd trip point. 1 vdd is below lvd trip point. individual register names and addresses: 1,e4h vlt_cmp : 1,e4h 7 6 5 4 3 2 1 0 access : por r : 0 bit name lvd bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 281 imo_tr 1,e8h 21.4.22 imo_tr internal main oscill ator trim register this register is used to manually center the internal main oscillator?s (imo) output to a target frequency. it is strongly recommended that you do not alter this register?s values except to load factory trim settings when changing imo range. when changing ranges, the new trim value for this range must be read from flash using a table read operation. the new value must be written at the lower frequency range. that is, when moving to a higher frequency range, change the imo_tr value and then change the range (slimo[1:0] in cpu_scr1). w hen moving to a lower frequency, change the range first and then update imo_tr. for additional information, refer to the register definitions on page 64 in the internal main oscillator chapter. 7:0 trim[7:0] the value of this register is used to trim the inter nal main oscillator. its val ue is set to the best value for the device during boot. individual register names and addresses: 1,e8h imo_tr : 1,e8h 7 6 5 4 3 2 1 0 access : por rw : 00 bit name trim[7:0] bit name description [+] feedback
282 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c ilo_tr 1,e9h 21.4.23 ilo_tr internal low speed oscillator trim register this register sets the adjustment for the internal low speed oscillator (ilo). it is strongly recommended that you do not alter this register?s freq trim[3:0] values. the trim bits are set to factory specifications and must not be changed. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. always write reserved bits with a value of ?0?. for additional information, refer to the register definitions on page 68 in the internal low speed oscillator chapter. 6 pd_mode this bit selects power down mode. setting this bit high disables oscillator and current bias, which results in slower startup time. power down mode: 0 partial oscillator power down fo r faster startup (100 na nominal). 1 full oscillator power down for lower power (0 na nominal). 5 ilofreq selects oscillator nominal frequency. 0 32 khz 1 1 khz 3:0 freq trim[3:0] these bits trim the oscillator frequency. individual register names and addresses: 1,e9h ilo_tr : 1,e9h 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 08 bit name pd_mode ilofreq freq trim[3:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 283 slp_cfg 1,ebh 21.4.24 slp_cfg sleep configuration register this register sets up the sleep duty cycle. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 77 in the sleep and watchdog chapter. 7:6 pssdc[1:0] sleep duty cycle. controls the ratios (in numbers of 32.768 khz clock periods) of ?on? time versus ?off? time for porlvd, bandgap reference, and pspump. 00b 1 / 256 (8 ms). 01b 1 / 1024 (31.2 ms). 10b 1 / 64 (2 ms). 11b 1 / 16 (500 s). individual register names and addresses: 1,ebh slp_cfg : 1,ebh 7 6 5 4 3 2 1 0 access : por rw : 0 bit name pssdc[1:0] bit name description [+] feedback
284 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c slp_cfg2 1,ech 21.4.25 slp_cfg2 sleep configuration register 2 this register holds the configuration for i2c sleep, deep sleep, and buzz. in the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 77 in the sleep and watchdog chapter. 3:2 alt_buzz[1:0] these bits control additional sele ctions for por/lvd buzz rates. 00 compatibility mode, buzz rate is determined by pssdc bits. 01 duty cycle is 1/32768. 10 duty cycle is 1/8192. 11 reserved. 1 i2c_on this bit enables the standby regulator in i2c sleep mode at a level sufficient to supply the i2c cir- cuitry. 0lso_off this bit disables the lso os cillator when in sleep state. individual register names and addresses: 1,ech slp_cfg2 : 1,ech 7 6 5 4 3 2 1 0 access : por rw : 0 rw : 0 rw : 0 bit name alt_buzz[1:0] i2c_on lso_off bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 285 slp_cfg3 1,edh 21.4.26 slp_cfg3 sleep configuration register 3 this register holds the configuration of the wakeup sequence taps. it is strongly recommended to not alter this register setting . in the table above, note that the reserved bit is a grayed table cell and is not described in the bit description section below . reserved bits must always be written with a value of ?0?. for additional information, refer to the register definitions on page 77 in the sleep and watchdog chapter. 6 dbl_taps when this bit is set all the tap values (t 0, t1, and t2) are doubled for the wakeup sequence. 5:4 t2tap[1:0] these bits control the duration of the t2-t4 sequence (see figure 10-2 on page 75 ) by selecting a tap from the wakeuptimer. note : the t2 delay is only valid for the wakeup sequence. it is not used for the buzz sequence. 00 1 s 01 2 s 10 5 s 11 10 s 3:2 t1tap[1:0] these bits control the duration of the t1-t2 sequence (see figure 10-2 on page 75 ) by selecting a tap from the wakeup timer. 00 3 s 01 4 s 10 5 s 11 10 s 1:0 t0tap[1:0] these bits control the duration of the t0-t1 sequence (see figure 10-2 on page 75 ) by selecting a tap from the wakeup timer. 00 10 s 01 14 s 10 20 s 11 30 s individual register names and addresses: 1,edh slp_cfg3 : 1,edh 7 6 5 4 3 2 1 0 access : por rw : 1 rw : 11 rw : 11 rw : 11 bit name dbl_taps t2tap[1:0] t1tap[1:0] t0tap[1:0] bit name description [+] feedback
286 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c imo_tr1 1,fah 21.4.27 imo_tr1 internal main oscillat or trim register 1 this register is used to fine tune the imo frequency. it is strongly recommended that the user not alter this register?s values . in the table above, note that reserved bits are grayed table cell s and are not described in the bit description section. reserv ed bits should always be written with a value of ?0?. for additional information, refer to the register definitions on page 64 in the internal main o scillator chapter. 7:0 finetrim[2:0] these bits provide ability to fine tune the imo frequency. these values are normally only changed by the os cillator-locking function. these are the lower 3 bits of the 11-bit oscillator trim. imo_tr holds the msb. individual register names and addresses: 1,fah imo_tr1 : 1,fah 7 6 5 4 3 2 1 0 access : por w : 0 bit name finetrim[2:0] bit name description [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 287 section f: glossary the glossary section explains the terminology used in this te chnical reference manual. glossary terms are characterized in bold, italic font throughout the text of this manual. a accumulator in a cpu, a register in which intermediate results are stored. without an accumulator, it would be necessary to write the result of each calculation (addition, subtraction, shift, and so on) to main memory and read them back. access to main memory is slower than access to the accu- mulator, which usually has direct paths to and from the arithmetic and logic unit (alu). active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. active low 1. a logic signal having its asserted state as the logic 0 state. 2. a logic signal having its logic 1 state as the lower voltage of the two states: inverted logic. address the label or number identifying the memory location (ram, rom, or register) where a unit of information is stored. algorithm a procedure for solving a mathematical problem in a finite number of steps that frequently involve repetition of an operation. ambient temperature the temperature of the air in a designated area , particularly the area surrounding the psoc device. analog as opposed to digital, signals that are on or off or ?1? or ?0?. analog signals vary in a continuous manner. see also analog signals . analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, multi-pole filters, gain stages, and much more. analog output an output that is capable of driving any voltage between the supply rails, instead of just a logic 1 or logic 0. analog signals a signal represented in a continuous form with respect to continuous times, as contrasted with a digital signal represented in a discrete (discontinuous) form in a sequence of time. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. and see boolean algebra . [+] feedback
288 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c glossary api (application pro- gramming interface) a series of software routines that comprise an interface between a computer application and lower-level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwar e applications. array an array, also known as a vector or list, is one of the simplest data structures in computer pro- gramming. arrays hold a fixed number of equally-sized data elements, generally of the same data type. individual elements are accessed by index using a consecutive range of integers, as opposed to an associative array. most high level programming languages have arrays as a built- in data type. some arrays are multi-dimensional, meaning they are indexed by a fixed number of integers; for example, by a group of two integers. one- and two-dimensional arrays are the most common. also, an array can be a group of capacitors or resistors connected in some common form. assembly a symbolic representation of the machine language of a specific processor. assembly language is converted to machine code by an assembler. usually, each line of assembly code produces one machine instruction, though the use of macros is common. assembly languages are consid- ered low level languages; where as c is considered a high level language. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock sig- nal. attenuation the decrease in intensity of a signal as a result of absorption of energy and of scattering out of the path to the detector, but not including the reduction due to geometric spreading. attenuation is usually expressed in db. b bandgap reference a stable voltage reference design that matches the positive temperature coefficient of v t with the negative temperature coefficient of v be , to produce a zero temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or inform ation processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss). it is sometimes represented more specifically as, for example, full width at half maxi- mum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. bias current the constant low level dc current that is used to produce a stable operation in amplifiers. this current can sometimes be changed to alter the bandwidth of an amplifier. binary the name for the base 2 numbering system. t he most common numbering system is the base 10 numbering system. the base of a numbering system indicates the number of values that may exist for a particular positioning within a numbe r for that system. for example, in base 2, binary, each position may have one of two values (0 or 1). in the base 10, decimal, each position may have one of ten values (0, 1, 2, 3, 4, 5, 6, 7, 8, and 9). bit a single digit of a binary number. therefore, a bit may only have a value of ?0? or ?1?. a group of 8 bits is called a byte. because the psoc m8c is an 8-bit microcontroller, the psoc native data chunk size is a byte. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 289 glossary bit rate (br) the number of bits occurring per unit of time in a bit stream, usually expressed in bits per second (bps). block 1. a functional unit that performs a si ngle function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital block or an analog block. boolean algebra in mathematics and computer science, boolean algebras or boolean lattices, are algebraic structures which "capture the essence" of the logical operations and, or and not as well as set the theoretic operations union, intersection, and complement. boolean algebra also defines a set of theorems that describe how boolean equations can be manipulated. for example, these theorems are used to simplify boolean equations which reduces the number of logic elements needed to implement the equation. the operators of boolean algebra may be repres ented in various ways. often they are simply written as and, or, and not. in describing circuits, nand (not and), nor (not or), xnor (exclusive not or), and xor (exclusive or) may also be used. mathematicians often use + (for example, a+b) for or and for and (for example, a*b) (since in some ways those operations are analogous to addition and multiplication in other algebraic structures) and repre- sent not by a line drawn above the expression being negated (for example, ~a, a_, !a). break-before-make the elements involved go through a disconnecte d state entering (?break?) before the new con- nected state (?make?). broadcast net a signal that is routed throughout the microcontroller and is accessible by many blocks or sys- tems. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations into which data is read or from which data is written. 2. a portion of memory set aside to store data, ofte n before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower t he output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically repre- sented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a common connection for a group of related devices. byte a digital storage unit consisting of 8 bits. c c a high level programming language. capacitance a measure of the ability of two adjacent conducto rs, separated by an insulator, to hold a charge when a voltage differential is applied between them. capacitance is measured in units of farads. capture to extract information automatically through t he use of software or hardware, as opposed to hand-entering of data into a computer file. [+] feedback
290 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c glossary chaining connecting two or more 8-bit digital blocks to form 16-, 24-, and even 32-bit functions. chaining allows certain signals such as compare, carry, enable, capture, and gate to be produced from one block to another. checksum the checksum of a set of data is generated by adding the value of each data word to a sum. the actual checksum can simply be the result sum or a value that must be ad ded to the sum to gen- erate a pre-determined value. chip a single monolithic integrated circuit (ic). see also integrated circuit (ic) . clear to force a bit/register to a value of logic 0. clock the device that generates a periodic signal wi th a fixed frequency and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. clock generator a circuit that is used to generate a clock signal. cmos the logic gates constructed using mos transistors connected in a complementary manner. cmos is an acronym for complementary metal-oxide semiconductor. comparator an electronic circuit that produces an output volt age or current whenever two input levels simul- taneously satisfy pre-determined amplitude requirements. compiler a program that translates a high level language, such as c, into machine language. configuration in a computer system, an arrangement of functional units according to their nature, number, and chief characteristics. configuration pertains to hardware, software, firmware, and documenta- tion. the configuration af fects system performance. configuration space in psoc devices, the register space accessed when the xio bit in the cpu_f register is set to ?1?. crowbar a type of over-voltage protection that rapidly places a low resistance shunt (typically an scr) from the signal to one of the power supply rails, when the output voltage exceeds a pre-deter- mined value. crystal oscillator an oscillator in which the frequency is controlled by a piezoelectric crystal. typically a piezoelec- tric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. d data bus a bidirectional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. data stream a sequence of digitally encoded signals used to represent information in transmission. data transmission the sending of data from one place to anoth er by means of signals over a channel. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 291 glossary debugger a hardware and software system that allows the user to analyze the operation of the system under development. a debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. decimal a base 10 numbering system, which uses the symbols 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9 (called digits) together with the decimal point and the sign symbols + (plus) and - (minus) to represent num- bers. default value pertaining to the pre-defin ed initial, original, or specific sett ing, condition, value, or action a sys- tem assumes, uses, or takes in the absence of instructions from the user. device the device referred to in this manual is the psoc chip, unless otherwise specified. die an unpackaged integrated circuit (ic), normally cut from a wafer. digital a signal or function, the amplitude of which is characterized by one of two discrete values: ?0? or ?1?. digital blocks the 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital logic a methodology for dealing with expressions containing two-state variables that describe the behavior of a circuit or system. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the ana- log-to-digital (adc) converter performs the reverse operation. direct access the capability to obtain data from a storage device, or to enter data into a storage device, in a sequence independent of their relative positions by means of addresses that indicate the physi- cal location of the data. duty cycle the relationship of a clock period high time to its low time , expressed as a percent. e emulator duplicates (provides an emulation of) the functi ons of one system with a different system, so that the second system appears to behav e similar to the first system. external reset (xres) an active high signal that is driven into t he psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. f falling edge a transition from a logic 1 to a logic 0. also known as a negative edge. feedback the return of a portion of the output, or processed portion of the output, of a (usually active) device to the input. filter a device or process by which certain frequency components of a signal are attenuated. [+] feedback
292 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c glossary firmware the software that is embedded in a hardware device and executed by the cpu. the software may be executed by the end user but it may not be modified. flag any of various types of indicators used for identification of a condition or event (for example, a character that signals the termination of a transmission). flash an electrically programmable and erasable, non volatile technology that provides users with the programmability and data storage of eproms, plus in-system erasability. nonvolatile means that the data is retained when power is off. flash bank a group of flash rom blocks where flash block numbers always begin with ?0? in an individual flash bank. a flash bank also has its own block level protection information. flash block the smallest amount of flash rom space that may be programmed at one time and the small- est amount of flash space that may be protected. a flash block holds 64 bytes. flip-flop a device having two stable states and two input terminals (or types of input signals) each of which corresponds with one of the two states. the circuit remains in either state until it is made to change to the other state by application of the corresponding signal. frequency the number of cycles or events per uni t of time, for a periodic function. g gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. ground 1. the electrical neutral line having the same potential as the surrounding earth. 2. the negative side of dc power supply. 3. the reference point fo r an electrical system. 4. the conducting paths between an electric circui t or equipment and the earth, or some con- ducting body serving in place of the earth. h hardware a comprehensive term for all of the physical parts of a computer or embedded system, as distin- guished from the data it contains or operates on, and the software that provides instructions for the hardware to accomplish tasks. hardware reset a reset that is caused by a circuit, such as a po r, watchdog reset, or external reset. a hardware reset restores the state of the device as it was when it was first powered up. therefore, all regis- ters are set to the por value as indicated in register tables throughout this manual. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 293 glossary hexadecimal a base 16 numeral system (often abbreviated and called hex), usually written using the symbols 0-9 and a-f. it is a useful system in computer s because there is an easy mapping from four bits to a single hex digit. thus, one can represent every byte as two consecutive hexadecimal digits. compare the binary, hex, a nd decimal representations: bin = hex = dec 0000b = 0x0 = 0 0001b = 0x1 = 1 0010b = 0x2 = 2 ... 1001b = 0x9 = 9 1010b = 0xa = 10 1011b = 0xb = 11 ... 1111b = 0xf = 15 so the decimal numeral 79 whose binary representation is 0100 1111b can be written as 4fh in hexadecimal (0x4f). high time the amount of time the signal has a value of ?1? in one period, for a periodic digital signal. i i2c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to con nect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building c ontrol electronics. i2c us es only two bidirectional pins, clock and data, both running at +5v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer?). idle state a condition that exists whenever user messages are not being transmitted, but the service is immediately available for use. impedance 1. the resistance to the flow of current caused by resistive, capacitive, or inductive devices in a circuit. 2. the total passive opposition offered to the flow of electric current. note the impedance is determined by the particular combination of re sistance, inductive reactance, and capacitive reactance in a given circuit. input a point that accepts data in a device, process, or channel. input/output (i/o) a device that introduces data into or extracts data from a system. instruction an expression that specifies one operation and identifies its operands, if any, in a programming language such as c or assembly. integrated circuit (ic) a device in which components such as resistors, capacitors, diodes, and transistors are formed on the surface of a single piece of semiconductor. interface the means by which two systems or devices ar e connected and intera ct with each other. [+] feedback
294 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c glossary interrupt a suspension of a process, such as the executi on of a computer program, caused by an event external to that process and performed in such a way that the process can be resumed. interrupt service rou- tine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning the device to the point in the program where it left normal program execution. j jitter 1. a misplacement of the timing of a transition from its ideal position. a typical form of corrup- tion that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the inter- val between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. k keeper a circuit that holds a signal to the last driven value, even when the signal becomes un-driven. l latency the time or delay that it takes for a signal to pass through a given circuit or network. least significant bit (lsb) the binary digit, or bit, in a binary number that re presents the least significant value (typically the right-hand bit). the bit versus byte distinction is made by using a lower case ?b? for bit in lsb. least significant byte (lsb) the byte in a multi-byte word that represents the least significant value (typically the right-hand byte). the byte versus bit distinction is made by using an upper case ?b? for byte in lsb. linear feedback shift register (lfsr) a shift register whose data input is generated as an xor of two or more elements in the register chain. load the electrical demand of a process expressed as power (watts), current (amps), or resistance (ohms). logic function a mathematical function that performs a digital operation on digital data and returns a digital value. lookup table (lut) a logic block that implements several logic functions. the logic function is selected by means of select lines and is applied to the inputs of the block. for example: a 2 input lut with 4 select lines can be used to perform any one of 16 logic functions on the two inputs resulting in a single logic output. the lut is a combinational device; therefore, the input/output relationship is contin- uous, that is, not sampled. low time the amount of time the signal has a value of ?0? in one period, for a periodic digital signal. low voltage detect (lvd) a circuit that senses vdd and provides an interrupt to the system when vdd falls below a selected threshold. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 295 glossary m m8c an 8-bit harvard architecture microprocessor. th e microprocessor coordinates all activity inside the psoc device by interfacing to the flash, sram, and register space. macro a programming language macro is an abstraction whereby a certain textual pattern is replaced according to a defined set of rules. the interpreter or compiler automatically replaces the macro instance with the macro contents when an instance of the macro is encountered. therefore, if a macro is used 5 times and the macro definition required 10 bytes of code space, 50 bytes of code space are needed in total. mask 1. to obscure, hide, or otherwise prevent informat ion from being derived from a signal. it is usu- ally the result of interaction with another signal, such as noise, static, jamming, or other forms of interference. 2. a pattern of bits that can be used to retain or suppress segments of another pattern of bits in computing and data processing systems. master device a device that controls the timing for data exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is designed primarily for cont rol systems and produ cts. in addition to a cpu, a microcontroller typically includes me mory, timing circuits, and i/o circuitry. the rea- son for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this, in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed signal the reference to a circuit containing both analog and digital techniques and components. mnemonic 1. a tool intended to assist the memory. mnemonics rely on not only repetition to remember facts, but also on creating associations between easy-to-remember constructs and lists of data. 2. a two to four character string repr esenting a microprocessor instruction. mode a distinct method of operation for software or hardware. for example, the digital block may be in either counter mode or timer mode. modulation a range of techniques for encoding information on a carrier signal, typically a sine-wave signal. a device that performs modulation is known as a modulator. modulator a device that imposes a signal on a carrier. mos an acronym for metal-oxide semiconductor. most significant bit (msb) the binary digit, or bit, in a binary number that represents the most significant value (typically the left-hand bit). the bit versus byte distinction is made by using a lower case ?b? for bit in msb. most significant byte (msb) the byte in a multi-byte word that represents t he most significant value (typically the left-hand byte). the byte versus bit di stinction is made by using an upper case ?b? for byte in msb. [+] feedback
296 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c glossary multiplexer (mux) 1. a logic function that uses a binary value, or address, to select between a number of inputs and conveys the data from the selected input to the output. 2. a technique which allows different input (or output) signals to use the same lines at different times, controlled by an external signal. multiplexing is used to save on wiring and i/o ports. n nand see boolean algebra . negative edge a transition from a logic 1 to a logic 0. also known as a falling edge. net the routing between devices. nibble a group of four bits, which is one-half of a byte. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or more characteristics of any entity such as voltage, current, or data. nor see boolean algebra . not see boolean algebra . o or see boolean algebra . oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. output the electrical signal or signals which ar e produced by an analog or digital block. p parallel the means of communication in which digital data is sent multiple bits at a time, with each simul- taneous bit being sent over a separate line. parameter characteristics for a given block that have either been characterized or may be defined by the designer. parameter block a location in memory where parameters for the ssc instruction are placed prior to execution. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd par- ity). path 1. the logical sequence of instructions executed by a computer. 2. the flow of an electrical signal through a circuit. pending interrupts an interrupt that has been triggered but has not been serviced, either because the processor is busy servicing another interrupt or global interrupts are disabled. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 297 glossary phase the relationship between two signals, usually the same frequency, that determines the delay between them. this delay between signals is ei ther measured by time or angle (degrees). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle rela- tive to a reference signal. pin a terminal on a hardware component. also called lead. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involves pin numbers as a link between schematic and pcb design (both being computer gener- ated files) and may also involve pin names. port a group of pins, usually eight. positive edge a transition from a logic 0 to a logic 1. also known as a rising edge. posted interrupts an interrupt that has been detected by the ha rdware but may or may not be enabled by its mask bit. posted interrupts that are not masked become pending interrupts. power on reset (por) a circuit that forces the psoc device to reset when the voltage is below a pre-set level. this is one type of hardware reset . program counter the instruction pointer (also called the program counter) is a register in a computer processor that indicates where in memory the cpu is executing instructions. depending on the details of the particular machine, it holds either the address of the instruction being executed or the address of the next instruction to be executed. protocol a set of rules. particularly the rules that govern networked communications. psoc? cypress semiconductor?s progra mmable system-on-chip (psoc) mixed-signal array. psoc? is a trademark of cypress. psoc blocks see analog blocks and digital blocks . psoc designer? the software for cypress? programmable system-on-chip technology. pulse a rapid change in some characteristic of a sig nal (for example, phase or frequency) from a base- line value to a higher or lower value, followed by a rapid return to the baseline value. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measure. r ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a known state. see hardware reset and software reset . resistance the resistance to the flow of electric current measured in ohms for a conductor. [+] feedback
298 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c glossary revision id a unique identifier of the psoc device. ripple divider an asynchronous ripple counter constructed of flip-f lops. the clock is fed to the first stage of the counter. an n-bit binary counter consisting of n flip-flops that can count in binary from 0 to 2 n - 1. rising edge see positive edge . rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. routine a block of code, called by another block of code, that may have some general or frequent use. routing physically connecting objects in a design according to design rules set in the reference library. runt pulses in digital circuits, narrow pulses that, due to non-zero rise and fall times of the signal, do not reach a valid high or low level. for example, a runt pulse may occur when switching between asynchronous clocks or as the result of a race condition in which a signal takes two separate paths through a circuit. these race conditions may have different delays and are then recom- bined to form a glitch or when the output of a flip-flop becomes metastable. s sampling the process of converting an analog signal in to a series of digital values or reversed. schematic a diagram, drawing, or sketch that details the elements of a system, such as the elements of an electrical circuit or the elements of a logic diagram for a computer. seed value an initial value loaded into a linear feedback shift register or random number generator. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occu rrence of two or more related activities in a single device or channel. set to force a bit/register to a value of logic 1. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift the movement of each bit in a word, one position to either the left or right. for example, if the hex value 0x24 is shifted one place to the left, it becomes 0x48. if the hex value 0x24 is shifted one place to the right, it becomes 0x12. shift register a memory storage device that sequentially shifts a word either left or right to output a stream of serial data. sign bit the most significant binary digit, or bit, of a sig ned binary number. if set to a logic 1, this bit rep- resents a negative quantity. signal a detectable transmitted energy that can be used to carry information. as applied to electronics, any transmitted electrical impulse. silicon id a unique identifier of the psoc silicon. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 299 glossary skew the difference in arrival time of bits transmitted at the same time, in parallel transmission. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. software a set of computer programs, procedures, and associated documentation concerned with the operation of a data processing system (for ex ample, compilers, library routines, manuals, and circuit diagrams). software is often written first as source code and then converted to a binary format that is specific to the device on which the code is executed. software reset a partial reset executed by software to bring pa rt of the system back to a known state. a soft- ware reset restores the m8c to a known state bu t not blocks, systems, peripherals, or registers. for a software reset, the cpu registers (cpu_a, cpu_f, cpu_pc, cpu_sp, and cpu_x) are set to 0x00. therefore, code execution begins at flash address 0x0000. sram an acronym for static random access memory. a memory device allowing users to store and retrieve data at a high rate of speed. the term static is used because, once a value has been loaded into an sram cell, it remains unchanged until it is explicitly altered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stack a stack is a data structure that works on the principle of last in first out (lifo). this means that the last item put on the stack is the first item that can be taken off. stack pointer a stack may be represented in a computer?s inside blocks of memory cells, with the bottom at a fixed location and a variable stack pointer to the current top cell. state machine the actual implementation (in hardware or software) of a function that can be considered to con- sist of a set of states through which it sequences. sticky a bit in a register that maintains its value past the time of the event that caused its transition has passed. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. switching the controlling or routing of signals in circuits to execute logical or arithmetic operations, or to transmit data between specific points in a network. switch phasing the clock that controls a given switch, phi1 or phi2, in respect to t he switched capacitor (sc) blocks. the sc blocks have two groups of switches. one group of these switches is normally closed during phi1 and open during phi2. the other group is open during phi1 and closed dur- ing phi2. these switches can be controlled in the normal operation, or in reverse mode if the phi1 and phi2 clocks are reversed. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. [+] feedback
300 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c glossary t tap the connection between two blocks of a device created by connecting several blocks/compo- nents in a series, such as a shift re gister or resistive voltage divider. terminal count the state at which a counter is counted down to zero. threshold the minimum value of a signal th at can be detected by the system or sensor under consider- ation. transistors the transistor is a solid-state semiconductor device used for amplification and switching, and has three terminals. a small current or voltage applied to one terminal controls the current through the other two. it is the key component in all modern electronics. in digital circuits, tran- sistors are used as very fast electrical switch es, and arrangements of transistors can function as logic gates, ram-type memory, and other devices. in analog circuits, transistors are essentially used as amplifiers. tri-state a function whose output can adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net . u uart a uart or universal asynchronous receiver-trans mitter translates between parallel bits of data and serial bits. user the person using the psoc device and reading this manual. user modules pre-build, pre-tested hardware/firmware periphe ral functions that take care of managing and configuring the lower level analog and digital bl ocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the regist ers in this bank are more likely to be modified during normal program execution and not just during initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v vdd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 or 3.3 volts. volatile not guaranteed to stay the same value or level when not in scope. vss a name for a power net meaning "voltage source." the most negative power supply signal. [+] feedback
psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c 301 glossary w watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. waveform the representation of a signal as a plot of amplitude versus time. x xor see boolean algebra . [+] feedback
302 psoc cy8ctmg20x and cy8ctst200 trm, document no. 001-53603 rev. *c glossary [+] feedback
303 index numerics 16-pin part pinout 19 24-pin part pinout 20 32 khz clock selection 67 32-pin part pinout 21 48-pin part pinout 22 a ack bit 240 acronyms 18 address bits in i2c_scr register 240 address spaces, cpu core 27 amux_cfg register 204 analog bit in int_clr0 register 243 in int_msk0 register 250 analog input, gpio 56 architecture psoc core 23 system resources 105 top level 14 truetouch system 83 b bank 0 registers 188 register mapping table 184 bank 1 registers 259 register mapping table 185 basic paging in ram paging 39 bias trim bits in ilo_tr register 282 bus error bit 240 bypass bit 261 byte complete bit 240 c calibrate0 function in srom 37 calibrate1 function in srom 37 carry bit 254 cdsx bits 208 chain bit 212 checksum function in srom 37 cin_en bit 213 cintx bits 208 cip_en bit 213 clksel bits 212 clock phase bit in spi_cr 192 clock polarity bit 192 clock rate bits 239 clock sel bit 261 clock, external digital 110 switch operation 110 clocks digital, see digital clocks cmp_cr0 register 104, 207 cmp_cr1 register 104, 208 cmp_lut register 104, 210 cmp_mux register 103, 206 cmp_rdc register 103, 205 cmp0d bit 205 cmp0l bit 205 cmp1d bit 205 cmp1l bit 205 cmpxen bits 207 cohm bit 217 cohs bit 217 colm bit 217 cols bit 217 comparators 101 architecture 101 register definitions 103 configuration register in spi spi_cfg register 150 control register in spi spi_cr register 149 conventions, documentation acronyms 18 numeric naming 17 register conventions 183 core, see psoc core cpinx bits 208 cpu core 27 instruction formats 30 instruction set summary 28?29 overview 27 register definitions 32 cpu speed bits 276 cpu_f register 32, 254 cpu_scr0 register 138, 258 cpu_scr1 register 65, 257 crstx bits 208 cs_cnth register 94, 216 [+] feedback
304 index cs_cntl register 94, 215 cs_cr0 register 92, 211 cs_cr1 register 93, 212 cs_cr2 register 93, 213 cs_cr3 register 94, 214 cs_slew register 219, 220 cs_stat register 95, 217 cs_timer register 95, 218 csd_cs_clk bit in cs_cr0 register 211 csd_mode bit in cs_cr0 register 211 csd_prsclk bit in cs_cr0 register 211 csout bits in cs_cr0 register 211 cur_pp register 42, 234 current page pointer in ram paging 40 d data 222, 223 data bits in pt_data0 register 222, 223 data bits in cs_cnth register 94, 216 in cs_cntl register 94, 215 in i2c_dr register 233, 241 in prtxdr register 59, 188 in spi_rxr register 148, 191 in spi_txr register 147, 190 in tmp_drx register 42, 266 data bypass in gpio 58 data registers in spi 147 development kits 16 digital clocks 109 architecture 109 internal low speed oscillator 110 internal main oscillator 109 register definitions 112 system clocking signals 109 digital io, gpio 56 documentation history 16 overview 13 drive mode 0 bits 259 drive mode 1 bits 260 e en bit in cs_cr0 register 211 enable bit 239 enable bits in mux_crx registers 271 in spi_cr register 192 enswint bit 52, 251 ep0_cnt register 174, 199 ep0_cr register 173, 177 ep0_drx register 174, 200 epx_cnt1 register 175, 176 eraseall function in srom 36 eraseblock function in srom 36 extclken bit 278 external digital clock 110 external reset 139 f fastslew bits 219 flash memory organization 35 freq trim bits for ilo_tr 282 fs_en bit 219 full-speed usb 165 architecture 165 memory arbiter 166 register definitions 171 suspend mode 168 usb sie 165 usb sram 166 g general purpose io 55 analog and digital input 56 architecture 55 block interrupts 57 data bypass 58 digital io 56 drive modes 60 interrupt modes 57 port 1 distinctions 56 register definitions 59 gie bit 255 gies bit 258 gpio bit in int_clr0 register 242 in int_msk0 register 250 gpio block interrupts 57 gpio, see general purpose io h help, getting development kits 16 support 16 upgrades 16 i i2c bit in int_clr0 register 242 in int_msk0 register 250 i2c slave 117 application overview 118 architecture 117 basic data transfer 118 basic io timing 130 clock generation timing 130 operation 118 register definitions 122 [+] feedback
305 index stall timing 132 status timing 131 i2c_cfg register 126, 239 i2c_dr register 129, 241 i2c_scr register 128, 240 icapen bit 204 idac_d register 97, 256 idacdata bits 256 idacen bit 213 idx_pp register 43, 236 ilo, see internal low speed oscillator imo, see internal main oscillator imo_tr register 281 imo_tr1 register 181 imodis bit 278 index memory page pointer in ram paging 41 inm bit 217 innx bits 206 inpx bits 206 ins bit 217 insel bit 212 instruction formats 1-byte instructions 30 2-byte instructions 30 3-byte instructions 31 instruction set summary 28?29 int sel bit 261 int_clr0 register 48, 49, 50, 71, 242, 244, 245 int_msk0 register 51, 52, 248, 249, 250 int_sw_en register 52, 251 int_vc register 52, 252 intcap bits 204 internal low speed oscillator 67 32 khz clock selection 67 architecture 67 in digital clocks 110 register definitions 68 internal m8c registers 27 internal main oscillator 63 architecture 63 in digital clocks 109 register definitions 64 interrupt controller 45 application overview 46 architecture 45 interrupt table 47 latency and priority 46 posted vs pending interrupts 46 register definitions 48 interrupt enables bits 189 interrupt modes in gpio 57 interrupt table 47 interrupts in ram paging 40 inv bit 212 io analog multiplexer 99 architecture 99 register definitions 100 io_cfg register 61, 272 iramdis bit 257 irange bit 213 iress bit 257 l low voltage detect (lvd) see por and lvd lrb bit 240 lsb first bit 192 lutx bits 210 lvd bit 280 lvdtben bits 279 m m8c, see cpu core mapping tables, registers 183 master function for spi 146 measurement units 17 memory arbiter in usb 166 mode bits in cs_cr0 register 211 mux_crx register 100, 270, 271, 277 mvi instructions in ram paging 40 mvr_pp register 43, 237 mvw_pp register 44, 238 n no buzz bit 276 numeric naming conventions 17 o one shot bit 221, 224, 225 osc_cr0 register 276 osc_cr2 register 65, 278 out_p1 register 113, 273, 274 overrun bit 192 overviews psoc core 23 register tables 183 system resources 105 truetouch system 83 p p10d bit 274 p10en bit 274 p12d bit 273 p12en bit 273 p14d bit 273 p14en bit 273 p16d bit 273 p16en bit 273 page bits in cur_pp register 234 in idx_pp register 236 [+] feedback
306 index in mvr_pp register 237 in mvw_pp register 238 in stk_pp register 235 pending interrupt bits 252 pgmode bits 254 pin behavior during reset 135 pin information, see pinouts pinouts 16-pin part 19 24-pin part 20 32-pin part 21 48-pin part 22 pmax_cur register 180 por and lvd 143 architecture 143 register definitions 144 porlev bits 279 pors bit 258 power modes system resets 141 power on reset (por) see por and lvd power on reset in system resets 139 ppm bit 217 pps bit 217 product upgrades 16 programmable timer 161 architecture 161 register definitions 163 protectblock function in srom 36 protocol function for spi 145 prtxdm0 register 60, 259 prtxdm1 register 60, 260 prtxdr register 59, 188 prtxie register 59, 189 pselect bit 239 psoc core architecture 23 overview 14 register summary 24 see also cpu core pssdc bits 283, 284, 285 pt_cfg register 163, 164, 221 pt_data1 register 164 ptx_data0 register 164, 223 ptx_data1 register 164, 222 pxd_en bit 213 r ram paging 39 architecture 39 basic paging 39 current page pointer 40 index memory page pointer 41 interrupts 40 mvi instructions 40 register definitions 42 stack operations 40 readblock function in srom 35 reference of all registers 187 register conventions 17, 187 register definitions comparators 103 cpu core 32 digital clocks 112 general purpose io 59 i2c slave 122 internal low speed oscillator 68 internal main oscillator 64 interrupt controller 48 io analog multiplexer 100 por and lvd 144 programmable timer 163 ram paging 42 sleep and watchdog 77 spi 147 supervisory rom 38 system resets 137 truetouch module 92 usb, full-speed 171 register mapping tables bank 0 registers 184 bank 1 registers 185 registers bank 0 registers 188 bank 1 registers 259 core register summary 24 internal m8c registers 27 maneuvering around 187 mapping tables 183 reference of all registers 187 system resources register summary 106 truetouch register summary 84 regulated io application overview 70 architecture 69 res_wdt register 77, 253 rloclk bit 212 rx reg full bit 192 s serial peripheral interconnect, see spi slave bit 261 slave function for spi 146 slave operation, i2c 118 sleep and watchdog 73 application overview 76 architecture 73 bandgap refresh 80 register definitions 77 sleep sequence 79 sleep timer 76 timing diagrams 79 wake up sequence 80 watchdog timer 81 sleep bit in cpu_scr0 register 258 in int_clr0 register 242 in int_msk0 register 250 [+] feedback
307 index sleep bits 276 sleep timer 76 slimo bit 257 slp_cfg register 77, 283, 284, 285 spi 145 architecture 145 configuration register 150 control register 149 data registers 147 master data register definitions 148 master function 146 protocol function 145 register definitions 147 slave data register definitions 148 slave function 146 timing diagrams 151 spi bit in int_clr0 register 242 in int_msk0 register 250 spi complete bit 192 spi timing diagrams spi mode timing 151 spim timing 152 spis timing 157 spi_cfg register 150, 261 spi_cr register 149, 192 spi_rxr register 148, 191 spi_txr register 147, 190 sram with usb 166 srom, see supervisory rom ss_ bit 261 ss_en_ bit 261 stack operations in ram paging 40 start bit 221, 224, 225 start, how to 16 stk_pp register 43, 235 stop bit 258 stop ie bit 239 stop status bit 240 summary of registers mapping tables 183 psoc core 24 system resources 106 truetouch system 84 supervisory rom architecture 33 calibrate0 function 37 calibrate1 function 37 eraseall function 36 eraseblock function 36 function descriptions 34 protectblock function 36 readblock function 35 swbootreset function 34 tableread function 36 writeblock function 35 swbootreset function in srom 34 switch operation in digital clocks 110 system resets 135 architecture 135 external reset 139 functional details 141 pin behavior 135 power modes 141 power on reset 139 register definitions 137 timing diagrams 139 watchdog timer reset 139 system resources architecture 105 overview 14, 105 register summary 106 t tableread function in srom 36 technical support 16 timer1/0 bits in int_clr0 register 243 in int_msk0 register 250 timing diagrams i2c slave 130 sleep and watchdog 79 spi 151 system resets 139 truetouch module 97 tmp_drx register 42, 205 transmit bit 240 trim bits in imo_tr register 281, 286 truetouch counter 90 truetouch module 85 architecture 85 register definitions 92 timing diagram 97 types of approaches 85 truetouch system architecture 83 overview 14, 83 register summary 84 tx reg empty bit 192 u units of measure 17 upgrades 16 usb 195 usb, see full-speed usb usb_cr0 register 171, 195 usb_cr1 register 180, 262 usb_sofx register 171, 193 usbio_cr0 register 172, 196 usbio_cr1 register 172, 197 v v monitor bit in int_clr0 register 243, 245 in int_msk0 register 250 vlt_cmp register 144, 280 vlt_cr register 144, 279 [+] feedback
308 index vm bits 279 w watchdog timer reset 139 wdrs bit 258 wdsl_clear bits 253 writeandverify function in srom 37 writeblock function in srom 35 x xio bit 254 xres reset 139 z zero bit 255 [+] feedback
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